Validation/VLSI CAD/Design Engineer

Hillsboro, OR 97123
  • Job Code
Job Description

By applying to this posting your resume and profile will become visible to Intel Recruiters / Sourcers and will allow them to consider you for current and future job openings aligned with the skills and positions mentioned above.

About DE organization:

Now is an exciting time for Intels Design Enablement Group! This position is within the Design Enablement (DE) organization of Technology Development (TD). At Intel, Design Enablement is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies and partner with Technology Development to deliver cost-effective, competitive design platform.

In this position you will help us with one or more of the following responsibilities:

  • Design and integration of Intels lead technology-development test chips.
  • Define and design test structures needed for process development.
  • Work with TD Process and device experts to define critical Design features and test structures to exercise on the test chips.
  • Develop CAD software/flows that automate physical layout of E-Test Structures
  • Develop layout verification software to implement process design rules using industry standard tools.
  • Digital system design using RTL for implementation through logic synthesis & automatic place-and-route
  • Validate design IP at the IP and system level
  • Develop and utilize various debug and validation tools and/or methodologies to implement validation plans to ensure a solid design

Behavioral traits that we are looking for:

  • Written and verbal communication skills
  • Teamwork, problem-solving, and data analysis
  • Ability to work across geographical locations

This is an entry level position and will be compensated accordingly.


You must possess at least one or more of the below minimum qualifications to be considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. The experience listed below should be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.

This requisition has the skillset of different positions under the same opening. Therefore, several hiring managers will have the opportunity to review your profile, if you have one or more of the listed requirements, feel free to apply, you will have the opportunity to showcase your resume to more managers at the same time, a great chance to apply and get matched.

Minimum skills and experience that will get you noticed:

You must have Bachelors degree, Master's degree OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or other related Electrical Scientific STEM field

6+ months of work/educational experience in one or more of the following areas:

  • Computer architecture, RTL, Verilog, System Verilog, exposure to OVM UVM
  • Chip floor planning, layout integration, layout design rules and schematic/layout comparison debug and validation
  • RTL based design, including DFT, system architecture, and integration of various IPs into subsystems
  • Algorithm and programming techniques.
  • Object oriented programming, data structures, algorithms and digital logic.
  • Programming or scripting in Python, Perl, Tcl, SKILL, C++, or Unix shell.

Preferred experience in one or more of the following areas:

  • Knowledge of semiconductor device physics, process scaling, and advanced technology nodes.
  • Industry-standard CAD tools for schematic entry, circuit simulation, custom layout, and design/layout verification, from vendors such as Cadence, Synopsys, and Siemens.
  • Design Compiler (DC), IC Compiler (ICC2), Fusion Compiler (FC), Genus, or Innovus
  • Layout verification using ICV/Calibre.
  • Pre-silicon or post-silicon validation/verification
  • Development of PCells or PyCells


Inside this Business Group

Manufacturing and Product Engineering (MPE) is responsible for test development across product segments, supporting 95% of Intel's revenue. We deliver comprehensive pre-production test suites and component/physical debug capabilities to enable high quality, high volume manufacturing.

Other Locations
US, California, Santa Clara; US, California, Folsom; US, Arizona, Phoenix; US, Texas, Austin;

Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.

Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Validation/VLSI CAD/Design Engineer

Hillsboro, OR 97123

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