Timing Modeling and Methodology CAD Engineer

Intel
San Jose, CA 95113
  • Job Code
    JR0200510
Job Description

The mission of Intels Programmable Solutions Group (PSG) is to drive the future for FPGAs and Structured ASICs technology/solutions around the globe.

With the Design Automation and Methodology Group, you'll be surrounded by some of the brightest minds/engineers in the world as we are responsible for FPGA design analysis tools and methodologies.

As a Senior Member of Technical Staff (Timing Modeling and Methodology CAD Engineer) you will be responsible for cell characterization and timing modeling methodology of ASIC, Custom, and Semi-Custom IP. You will work with teams of experienced engineers to develop and support tools and methodologies for industry leading FPGA designs.


Qualifications

You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Education

Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

Minimum Qualifications

  • 5+ years of design automation experience.

Preferred Qualifications

  • 8+ years of design automation experience.

  • Experience with Python/TCL/Perl and/or programming algorithms.

  • Experience using network of Unix servers and job dispatcher tools on many machines efficiently.

  • Experience with cell characterization, circuit design, circuit simulation, static timing analysis and timing methodologies.

  • Experience with industry-standard cell characterization tools and static timing analysis tools.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.



Other Locations

US, California, Santa Clara;US, Texas, Austin


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Before you go...

Our free job seeker tools include alerts for new jobs, saving your favorites, optimized job matching, and more! Just enter your email below.

Share this job:

Timing Modeling and Methodology CAD Engineer

Intel
San Jose, CA 95113

Join us to start saving your Favorite Jobs!

Sign In Create Account