Timing Design Automation Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0189572
Job Description

Responsibilities of the role include, although not limited to:

  • Work closely with design teams to understand and debug Static Timing Analysis tool/flow/methodology issues
  • Define/Maintain/Document clear distinction between the project required code and the global code for all Intel BUs
  • Create and maintain flows and scripts to support Static Timing Analysis specific to Server/IP needs
  • Engage with vendors to drive tool quality improvements and fixes
  • Drive Static Timing Analysis to improve flows for deep submicron designs
  • Own regression and testing of design testcases to improve quality of flows deployed to design team

In addition to the qualifications listed below, the ideal candidate will also have:

  • Strong communication and written skills


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

The candidate must have a Bachelor's degree in Electrical/Computer Engineering, Computer Science or related major with 3+ years experience -OR- Master's degree in Electrical/Computer Engineering, Computer Science or related major with 2+ years experience in the following:

  • Static timing analysis (STA) tools and flow
  • Programming in TCL

Preferred Qualifications:

  • Experience programming in Perl/Python
  • Experience with Timing/Power ECO flows

Inside this Business Group

Product Enablement Solutions Group (PESG) is one of the key pillars, enabling Intel product design teams get to market faster with winning leadership products.



Other Locations

US, California, Folsom;US, Oregon, Hillsboro;US, Texas, Austin



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Timing Design Automation Engineer

Intel
Santa Clara, CA 95050

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