Test Chip Package Architect

Intel
Santa Clara, CA 95050
  • Job Code
    JR0194811
Job Description

The world is transforming and so is Intel!  Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower peoples digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver solutions for products that impact customers lives? If so, Come join us to do something wonderful!

In this position, you will be a part of the testchip team in IPG. This team develops testchips to validate IP for future Intel products.

Responsibilities will include but not limited to:

  • Cordinate package architecture and design efforts for the IPG testchip roadmap
  • Execute package design to meet overall package performance and specification and realize technology certification through layout design and test vehicle design.
  • Provide inputs to package design teams
  • Work directly with IP teams to gather requirements and capabilities for IP blocks
  • Develop post-silicon strategies for HVM and bench level testing
  • Coordinate with board design teams to insure the IP and testchip requirements are met
  • Regularly review and provide input on board designs and package designs
  • Collaborate with broad team of testchip partners to insure successful testchip power-on


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must have a Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 4+ years of experience - OR - Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 3+ years of experience in:

  • Platform and system design
  • Signal integrity and power delivery
  • Assembly (electronic packaging) and substrate manufacturing technologies

Preferred Qualifications: experience with:

  • Silicon floor planning and development
  • Cadence/Mentor package/board design tools.

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.



Other Locations

US, Arizona, Phoenix;US, Oregon, Hillsboro;US, Texas, Austin


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Test Chip Package Architect

Intel
Santa Clara, CA 95050

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