Technical Lead - SERDES Sub-system Emulation Design

Intel
San Jose, CA 95113
  • Job Code
    JR0169951
Job Description

As a member of Intel's Programmable Solutions group, the candidate will be responsible for developing an IP prototyping platform with a focus on FPGA interface design, verification, and validation, for Intel's  high speed SERDES products. 

In this role as Technical Lead FPGA Design - SERDES Sub-system IP Prototyping, you must possess a solid experience base in
Field Programmable Gate Array RTL (Register Transfer Level) development and logic synthesis as well as willing to excel in matters of communication. Furthermore, while our team will depend on your contribution as a technical lead, we will also depend on you as a product evangelist, and technical expert who is determined to achieve successful outcomes. Still interested? Please read the responsibilities and qualifications indicated below and apply as soon as possible.

Structured ASIC team: 

This is a structured ASIC team under Intels PSG is targeting 5G, cloud computing and high end consumer application space. Intel eASIC devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs bridging the gap between FPGA and Custom ASIC. 

Learn more about us:  

https://www.intel.com/content/www/us/en/products/programmable/fpga-vs-structured-asic.html 

https://www.intel.com/content/www/us/en/design/products-and-solutions/structured-asics/overview.html

Responsibilities:

 

 

  • Develop a custom Double Data Rate interface on a Field Programmable Gate Array using Verilog/System Verilog to interface with a Serializer/Deserializer IP testchip: Micro-architecture, Front-end Design, Verification and Board Validation 

  • Productize the interface as an integratable IP for internal and external customers. 

  • Create a reference design and lead the execution of a hardware validation plan. 

  • Generate collateral (Field Programmable Gate Array reference design, documentation and training) 

  • Lead the evolution (revolution) of the interface in subsequent product generations. Provide architectural input in the design/integration of Serializer/Deserializer IP in a programmable SoC environment 

  • Support customers with implementation of their logic to be tested with the DDR interface. 

  • Mentor/lead team members to execute on the interface.

      


Qualifications

Qualifications

You must possess the minimum qualifications to be initially considered for this position Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates
 

Minimum Education Requirement:
Bachelors degree in Electrical Engineering, Electrical Electronics, Computer Engineering, or related field

Minimum Qualifications:
10+years of expertise in Field Programmable Gate Array RTL (Register Transfer Level) development, verification and FPGA tools, Intel Quartus preferred.
10+years of experience in FPGAs or Application Specific Integrated Circuit , Serializer/Deserializer and networking applications.
5+ years of lab experience handling boards and test equipment such as oscilloscopes
7+ years of experience in programming and data analysis with Python or Matlab or Perl or C++ or any Object-Oriented language
2+ years of experience in Serializer/Deserializer IP architecture and implementation

Preferred Qualifications:

  • Experience in digital design
  • Familiar with MS Office Suite
  • Good logical thinking and communication skills

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Technical Lead - SERDES Sub-system Emulation Design

Intel
San Jose, CA 95113

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