Technical Lead Applications

San Jose, CA 95113
  • Job Code
Job Description

We are a global leader, creating world-changing technology that enables progress and enriches lives. Intel is at the intersection of several technology inflections artificial intelligence, 5G network transformation, and the rise of the intelligent edge- that together will shape the future of technology.

As a member of Intel's Programmable Solutions Group, you will use your knowledge of Logic Design, Verification, high speed IO/SERDES technology to lead efforts at a system level in enabling customers, both internal and external, to use the Structured ASIC technology. The position requires a self-driven candidate with deep knowledge in design, verification and communication interfaces, coupled with good communication skills.

Structured ASIC team: 

This is a structured ASIC team under Intels PSG and is targeting 5G, cloud computing and high end consumer application space. Intel eASIC devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs bridging the gap between FPGA and Custom ASIC. 

Learn more about us:


  • Provide hands-on applications leadership to internal and external customer programs pre and post silicon.
  • Manage/Develop collaterals such as HandBook, DataSheet, and Application notes
  • Create protocol specific use models. Perform protocol specific characterization and author characterization reports
  • Work with IP teams and customers to ensure proper usage of the SERDES for various applications and protocols
  • Define methodology for high speed serial IO measurements
  • Validate PCS and PMA blocks of the transceiver
  • Leading and dotted line managing the characterization team
  • Engaging with key customers to explain current and future SERDES architectures and requirements
  • Gather requirements for next generation SERDES and demonstrating technology capability
  • Lead the advanced customer support and design win effort as it relates to SERDES Design, Simulation, Bring Up Characterization, and Evaluation
  • Train and provide engineering support to Intel's worldwide customers and Applications team


You must possess the minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Education Requirements:

Bachelors degree in Electrical Engineering, Electrical Electronics or Computer Engineering with 15 plus years of experience or Masters degree in Electrical Engineering, Electrical Electronics or Computer Engineering with 10 plus years of experience

Minimum Qualifications:

  • 15+ years of experience in design,  development, implementation, and application of ASICs including high speed IO and SERDES
  • 10+ years of experience in FPGAs or ASICs, SERDES and networking applications
  • 5+ years of SERDES and protocols, such as PCI Express, or 10GBASE-KR/SR/MR/ER/LR, 25GBASE-KR, or JESD 204X, or CPRI/OBSAI, or DisplayPort or HDMI or VbyOne
  • 7+ years of experience in programming and data analysis with either Python, Matlab, Perl, C++ or any Object-Oriented language
  • 5+ years of experience in SI Concepts, including sources and causes of noise and jitter
  • 2+ years of experience in communication systems theory relating to SERDES
  • 2+ years of experience in SERDES IP architecture and implementation
  • 2+ years of experience in testing equipment, such as high-speed oscilloscopes BERTs and VNA

Preferred Qualifications:

  • Experience in analog and digital design

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Technical Lead Applications

San Jose, CA 95113

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