System Validation Engineer

San Jose, CA 95113
  • Job Code
Job Description

Intel is a global leader, creating world-changing technology that enables progress and enriches live. We are at the intersection of several technology inflections artificial intelligence, 5G network transformation, and the rise of the intelligent edge- that together will shape the future of technology.

The Programmable Solutions Group is responsible for delivering state of the art FPGA system solution. As part of High-speed IO validation team, we develop extensive firmware stack for enablement of cutting-edge DDR/LPDDR subsystem. The engineer is expected to closely work with pre-silicon firmware development and verification team to develop DDR firmware code, debug routines and is responsible for bringing up the firmware on silicon during post silicon phase. The engineer will act as a triage between post silicon validation team and pre-silicon development team to debug, validate and characterize firmware for different protocols. The engineer needs to have good knowledge and working experience in memory related technologies and deep knowledge of the JEDEC specifications and IO PHY training steps, as well as pre and post silicon debugging experience.

Your responsibilities will include:

  • Support silicon validation.
  • Bring up and debug DDR firmware on silicon
  • Review firmware spec and provide feedback to team
  • Develop firmware functions and pass C language linting
  • Coverity check and code review with team
  • Perform unit and system level testing including failure analysis and debug of product issues as part of development and validation phases
  •  Develop test plan on both unit testing and pre-silicon verification
  • Execute test plan. Debug in RTL simulation. Maintain regression
  •  Support Emulation team for testing and debugging


Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Education Requirement

BS in Computer Science or Electrical Engineering, or related field. If you have a Masters degree in Computer Science or Electrical Engineering or related field, you must have 3+ years of experience in digital logic design

Minimum Qualifications:

  • 6+ years of experience in digital logic design
  •  3+ years of experience in memory technologies.
  • 3+ years of post-silicon bring up and debug experience
  • 3+ years of experience or deep knowledge of DDR/LPDDR DRAM
  • 1+ years of experience in translating JEDEC specifications related to Memory and MIPI protocols into algorithms and drive hardware assisted training algorithm implementation
  • 3+ years of RTL simulation and debugging
  • 3+ years of firmware development and unit testing experience (C, GCC, Assembly)
  • 3+ years of experience in tools and scripting (Python, shell) experience

Preferred Qualifications

Experience with DDR/LPDDR DRAM and IO PHY training knowledge and experience
Expertise in Software Languages, such as; Python, C++, Verilog

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Other Locations

US, California, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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System Validation Engineer

San Jose, CA 95113

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