Structural/Physical Design Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0188343
Job Description

At Intel, we work every single day to design and manufacture silicon products as the fundamental building blocks that empower peoples digital lives. Do you love Contributing to cutting edge IP technology that are efficiently powering up your laptop? Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross-functional teams to deliver IP solutions for products that impact customers lives?

Intel's Power Sensor and Interconnect IP team under the Foundation IP Group (FIG) is looking for an experienced SOC design engineer to work on advanced I/O design for Intels IDM chiplet strategy. Candidate would work with a world class team on the interconnect IP for connecting up chiplets in Intels advanced packaging technology.

This high-speed IO is critical for delivering high bandwidth data to the various processing dies in our SOCs.

Responsibilities include but are not limited to:

  • Covers the complete semiconductor value chain for chip implementation.
  • Works closely with frontend (= wafer technology) and backend (= package technology) experts
  • Understanding of critical dependencies across domains
  • Conducts or participates in multidisciplinary research in the design, development, testing and utilization of information processing hardware and/or electrical components, mechanisms, materials, and/or circuitry, processes, packaging, and cabinetry for central processing units (CPUs) and/or peripheral equipment
  • Prepares specifications, evaluates vendors, and analyzes test reports
  • Ensures products conform to standards and specifications
  • Develops plans and cost estimates and assesses projects to analyze risk
  • Develops procedures, analysis and design for computer components, products, and systems
  • Initiates, guides, and coordinates overall design and development of new ideas and products
  • Responds to customer/client requests or events as they occur
  • Develops solutions to problems utilizing formal education and judgments


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

The candidate must have a Bachelor's degree in Computer/Electrical Engineering or Computer Science and 5+ years of experience -OR- a Master's Degree in Computer/Electrical Engineering or Computer Science and 3+ years of experience -OR- a PhD in Computer/Electrical Engineering or Computer Science and 1+ years of industry experience with:

  • Digital design backend tools tools viz. Design Compiler, IC Compiler2, Fusion Compiler, PrimeTime, Conformal, Redhawk and other sign-off tools
  • Complex SoCs, CTS, different clocking techniques in ICC for skew and delay balancing, multiple clock complexity, PnR congestion analysis, analysis and resolving floorplanning issues, UPF (Low power design techniques) and hand-on experience of digital design sign-off tools

Preferred Qualifications:

  • Working on 7nm technology and below
  • Experience with Synopsys PnR tool suite
  • Have participated in multiple complete rtl2gds2 implementation in block or full-chip level upto tape-out
  • Expertise in scripting using TCL, Perl and shell

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Structural/Physical Design Engineer

Intel
Santa Clara, CA 95050

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