Static Timing Analysis Engineer

Austin, TX
  • Job Code
    200046450
Summary

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. Joining this group means you'll be crafting and building the technology that fuels Apple's devices. Together, we enable our customers to do all the things they love with their devices.

In this role, you will be responsible for all aspects of timing including, working with designers for timing changes, helping construct/modify flows, timing analysis and timing closure

Key Qualifications

  • Working with design teams to understand and debug constraints, facilitate logic changes to improve timing
  • Working with Physical Design and Logic Design teams, highlighting issues
  • Help create timing ECO's for project tapeout
  • We value the ability to create and maintain scripts and methodologies for analysis and runs
  • Document and help with guidelines and specs
  • Deep analysis of timing paths to identify key issues is critical
  • Implement timing infrastructure
  • Good communicator who can accurately describe issues and follow them through to completion. Your attention to details will be instrumental to success

Description

You will have 5-10 years of hands on experience in STA
Familiar with timing of large high-performance SoC designs in sub-micron technologies.
Timing Margin Fundamentals from synthesis to signoff
Be proficient in STA and standards for timing closure, and have a deep understanding of noise, cross-talk, and OCV effects, among others
Familiar with circuit modeling, including SPICE models and worst-case corner selection. Strong programming skills with Perl, TCL
Timing Flow using industry standard tools
Experience with STA on large, complex designs and Multi-Scenario Timing Closure
Familiarity with ECO techniques and implementation

Education & Experience
- MSEE or equivalent is required

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Static Timing Analysis Engineer

Apple, Inc.
Austin, TX

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