Standard Cell Library Pathfinding & DTCO Lead

Intel
Hillsboro, OR 97123
  • Job Code
    JR0153643
Job Description

Advanced Design Group under Design Enablement in Technology Development has primary focus of Design-Technology Co-optimization (DTCO) and Foundational IP development to support both the Technology Development organization and Intels IP/Product design teams. Advanced power, performance and area (PPA) analyses are conducted across domains to guide Technology Development's research, pathfinding and technology definition.
 

Library Technology Group in Advanced Design is looking for a highly motivated and experienced individual to lead the pathfinding, development and optimization of standard cell libraries to enable best-in-class IP and product design on all generations of Intel technology.

As a technical lead of library pathfinding team, you are responsible for leading the standard cell pathfinding activities (cell layout architecture and modeling) with active collaboration with process technologists, product design stake holders, and EDA vendors to achieve best-in-class cell/block level PPA and competitive EoU (Ease of Use) through DTCO.

You will also be responsible for leading the standard cell benchmarking and competitive analysis activities and driving technology enhancements for FIP (foundation IP) leadership.

Other responsibilities include (but not limited to) supporting test-chip planning and Si validation of standard cells to track yield, Vmin and power/performance.

#designenablement

@designenablemnt
#LI-JR1


Qualifications

You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Minimum Requirements

Ph.D. in Electrical Engineering, Computer Science, Computer Engineering or other related field of study

Preferred Requirements

  • Minimum of 10 years of experience in foundational IP pathfinding in DTCO,  silicon implementation, or technology development

  • Successful experience in leading std cell library pathfinding and definition to optimize PPA through DTCO on advanced technology nodes strongly preferred

  • In-depth knowledge in digital design including CMOS combinatorial logic and sequential circuit and layout, and familiarity with design tradeoffs as well as standard cell modeling, extraction and characterization highly desired

  • Experience in EDA tool/flow/methodology, product and IP developments

  • Familiar with foundry ecosystem and benchmarking practice

  • Excellent communication and interpersonal skills to champion initiatives internally and externally, and for effective communication with executive management and external partners

  • Technical, analytical and cross-functional collaboration skills

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth



Other Locations

US, Arizona, Phoenix;US, California, Santa Clara



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter....

Before you go...

Our free job seeker tools include alerts for new jobs, saving your favorites, optimized job matching, and more! Just enter your email below.

Share this job:

Standard Cell Library Pathfinding & DTCO Lead

Intel
Hillsboro, OR 97123

Join us to start saving your Favorite Jobs!

Sign In Create Account