Sr. Test Engineering Manager

Intel
San Jose, CA 95113
  • Job Code
    JR0175782
Job Description

Intel is a global leader, creating world-changing technology that enables progress and enriches live. We are at the intersection of several technology inflections artificial intelligence, 5G network transformation, and the rise of the intelligent edge- that together will shape the future of technology.

Our team is Structured ASIC Manufacturing Engineering (SAME), and we provide manufacturing support to large group within SPG. SAME supports a wide range of FPGA base arrays with customized ASIC designs to achieve low cost, power and NRE to our customers (basically to structure customer ASIC designs on a FPGA base array).

As the Senior Test Engineering Manager for our team, you will be responsible for the following:

  • Leading the ePG (eASIC Products Group) local and remote Test Engineering team to develop and manufacture complex SOC devices on leading edge process and package technologies.
  • Managing the product life-cycle through definition, design, tapeout, prototype, qualification, and production release, and subcontractor qualification.
  • Collaborating with Engineering on new product development, DFT/DFM, package design, ATE test development, and new technology qualification and characterization.
  • Driving pathfinding for new technologies, capabilities, efficiencies and scale. Define test strategies to support best solution to BU roadmap.
  • Supporting the company's revenue and profitability plan by managing all product technical issues, product cost reduction, yield improvement, product qualification, and product quality.
  • Supporting the corporate Quality objectives by implementing a scalable process for high quality/high volume products and addressing customer RMA/FA requests in a satisfactory and timely manner.
  • Managing Test Engineering team to execute daily activities, priorities and providing mentorship to enhance team technical competence. Be prepared/capable of providing ongoing leadership to the Test Engineering team, including participation in hands-on test development and guidance.
  • Communicating with Sr. management & cross-functional teams and address business urgencies with efficiency.


Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
 

Minimum Education Requirement

Bachelors Degree in Electrical Engineering

Minimum Qualifications

10+ years of experience in the semiconductor industry in the following areas;
Experience with ATE hands-on test development experience, SerDes DFT/test knowledge, and good understanding of device physics

Experience in the IC process, assembly, and test (board level experience a plus). Strong emphasis on leading edge complex SOC DFT/DFM, ATE test development, and manufacturing.
Experience in project management in cross-functional work environments
 

Preferred Qualifications

Masters degree in Electrical Engineering

This position is not eligible for Intel immigration sponsorship.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Sr. Test Engineering Manager

Intel
San Jose, CA 95113

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