Sr Member of Technical Staff- SERDES Architect

Intel
San Jose, CA 95113
  • Job Code
    JR0186584
Job Description

Job Description

We are a global leader, creating world-changing technology that enables progress and enriches lives. Intel is at the intersection of several technology inflections - artificial intelligence, 5G network transformation, and the rise of the intelligent edge- that together will shape the future of technology.

As a member of Intel's Programmable Solutions Group, you will use your knowledge of high speed IO/SERDES technology, AIB and DDR to lead efforts for building state of the art SOC and enabling customers, both internal and external, to use the Structured ASIC technology. The position requires a self-driven candidate with deep knowledge in design, verification and communication interfaces, coupled with good communication skills.


Structured ASIC team:

This is a structured ASIC team under Intel's PSG is targeting 5G, cloud computing and high-end consumer application space. - Intel eASIC devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs bridging the gap between FPGA and Custom ASIC.

Learn more about us:

https://www.anandtech.com/show/16266/intels-new-easic-n5x-series-hardened-security-for-5g-and-ai-through-structured-asics

https://www.intel.com/content/www/us/en/products/programmable/fpga-vs-structured-asic.html

https://www.intel.com/content/www/us/en/design/products-and-solutions/structured-asics/overview.html


Responsibilities

  • Provide hands-on applications leadership to internal and external customer programs with SERDES arch and other IO interface IP procurement.
  • Manage/Develop collaterals such as HandBook, DataSheet, and Application notes.
  • Work with IP teams and customers to ensure proper usage of the SERDES for various applications and protocols.
  • Dictate design spec based on uses cases for PCS and PMA blocks of the transceiver.
  • Engaging with key customers to explain current and future SERDES architectures and requirements.
  • Gather requirements for next generation SERDES and demonstrating technology capability.
  • Support methodology for high speed serial IO measurements and Leading the characterization team.
  • Lead the advanced customer support and design win effort as it relates to SERDES Design, Simulation, Bring Up Characterization, and Evaluation
  • Train and provide engineering support to Intel's worldwide customers and Applications team

 

 


Qualifications

Qualifications

 

Minimum Qualifications
 

  • 7+ years of experience in FPGAs or ASICs, SERDES and networking applications.
     
  • Experience with SERDES and protocols, such as PCI Express, or 10GBASE-KR/SR/MR/ER/LR, 25GBASE-KR, or JESD 204X, or CPRI/OBSAI, or DisplayPort or HDMI or VbyOne.
     
  • Experience in programming and data analysis with either Python, Matlab, Perl, C++ or any Object-Oriented language
     
  • Experience with experience in SI Concepts, including sources and causes of noise and jitter
     
  • Experience with experience in communication systems theory relating to SERDES, SERDES IP architecture and implementation
     
  • Experience with experience in testing equipment, such as high-speed oscilloscopes, BERTs and VNA

Preferred Qualifications

  • Experience with DDR and AIB

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Sr Member of Technical Staff- SERDES Architect

Intel
San Jose, CA 95113

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