Sr Member of Technical Staff - Applications Engineer

Intel
San Jose, CA 95113
  • Job Code
    JR0186585
Job Description

We are a global leader, creating world-changing technology that enables progress and enriches lives. Intel is at the intersection of several technology inflections - artificial intelligence, 5G network transformation, and the rise of the intelligent edge- that together will shape the future of technology.

As a member of Intel's Programmable Solutions Group, in this role the candidate will use knowledge of Post-Si validation, SERDES, and Signal integrity and power integrity to validation or new and next generation SOC products. The candidate will interface with other teams related to board design and packaging to lead efforts at a system level in enabling customers, both internal and external, to use the Structured ASIC technology. The candidate should also be familiar with lab measurements and debug.

Structured ASIC team:

This is a structured ASIC team under Intel's PSG is targeting 5G, cloud computing and high-end consumer application space. Intel eASIC devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs bridging the gap between FPGA and Custom ASIC.

Learn more about us:

https://www.anandtech.com/show/16266/intels-new-easic-n5x-series-hardened-security-for-5g-and-ai-through-structured-asics
https://www.intel.com/content/www/us/en/products/programmable/fpga-vs-structured-asic.html
https://www.intel.com/content/www/us/en/design/products-and-solutions/structured-asics/overview.html

Responsibilities:

  • Drive post-silicon debug to root cause and provide resolution.
  • Work on improving validation infrastructure including: equipment, automation, scripting, fixtures and lab-setup.
  • Lead effective cross-functional efforts for process improvements, technical initiatives and resolutions.
  • Define methodology for high speed serial IO measurements. Validate PCS and PMA blocks of the transceiver.
  • Bring-Up characterization and evaluation Boards.
  • Train and provide engineering support to Intel's worldwide customers and Applications team.
  • Work in the lab to confirm some of the simulation findings.
  • Perform protocol specific characterization and author characterization reports.
  • Work with IP teams and customers to ensure proper usage of the SERDES for various applications and protocols.


Qualifications

Minimum Education Requirements

Bachelors' degree in Electrical Engineering, Electrical Electronics or Computer Engineering with 10 plus years of experience or Masters' degree in Electrical Engineering, Electrical Electronics or Computer Engineering with 7 plus years of experience.

Minimum Qualifications

Must have 7+ years experience in the following:

  • Power-on, System and functional level testing.
  • Good understanding of SOC architecture including ARM processors.
  • Experience in SI Concepts, including sources and causes of noise and jitter.
  • Solid background in transmission line theory, electro magnetics, layout - both packaging and PCB.
  • Design aspects, implementation and applications of high speed SERDES, 54G+ including PAM4.
  • SERDES and protocols such as PCI-Express or 10GBASE-KR/SR/MR/ER/LR, 25GBASE-KR or JESD204x or CPRI/OBSAI or DisplayPort or HDMI or VbyOne etc.
  • Communications System Theory as it pertains to SerDes specifically, including PLLs and Timing Recovery (CDR).
  • Hands on experience with test equipment such as high speed oscilloscopes, BERTs and VNA.
  • SERDES applications / characterization.

Preferred Qualifications
 

  • Throughput and coverage improving Test/Automation experience.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Sr Member of Technical Staff - Applications Engineer

Intel
San Jose, CA 95113

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