Sr. Mask Designer

Intel
San Jose, CA 95113
  • Job Code
    JR0198702
Job Description

The mission of Intels Programmable Solutions Group (PSG) is to drive the future for FPGAs and Structured ASICs technology/solutions around the globe.

You will be surrounded by some of the brightest minds/engineers in the world with the SJ Custom Layout Team as we are responsible for providing full custom analog, mixed signal and digital layout using cutting edge technologies to support key Intel FPGA products.

As a Sr. Mask Designer, you will be the primary owner of full custom design blocks, provide accurate schedule forecast, design layout with high quality floorplan,

wire plan to meet performance, reliability, design rule and integration requirements.  The work assignment often requires overseeing multiple layout designers and collaboration with design automation team to enhance layout tool/flow efficiency.


Qualifications

You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

7+ years of experience in analog, mixed signal and digital custom layout

7+ years of experience with layout design and verification tools

5+years of experience in layout with advanced technology nodes, 20nm and below finFet technologies

 Preferred Qualifications:

10+ years of custom layout experience

Strong analog layout skills, including basic analog structures, layout skills in matching, multiple power domain, high current, high voltage and high-speed designs

Experience in floorplan, power plan, routing plan of complex analog, mixed signal and custom digital layout

Experience with providing and maintaining layout schedules

Experience of leading a design: delegate daily tasks, provide technical guidance and review layout quality

Experience with Virtuoso tool usage

Experience with Unix

Experience with basic programming

Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

This position is not eligible for Intel immigration sponsorship

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.



Other Locations

US, California, Santa Clara


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Sr. Mask Designer

Intel
San Jose, CA 95113

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