Sr. CAD Engineer, Silicon Learning and Static Timing Analysis

Cupertino, CA 95014
  • Job Code
    200283212
Summary

Summary

Posted: Aug 31, 2021

Role Number:200283212

Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As p...Summary

Summary

Posted: Aug 31, 2021

Role Number:200283212

Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Engineering Group, you'll help design and manufacture our next-generation silicon, providing the high-performance, power-efficient processors, graphics and systems-on-chip (SoCs) which have come to define Apple products. In this critical role, you will be responsible for analyzing silicon performance data to incorporate learning back into static timing analysis and design closure methodologies to drive continuous improvements in Apple products. Together, you and your team will enable our customers to do all of the things they love with their devices and some things that they haven't yet imagined to be possible!

Key Qualifications

  • The ideal candidate will have 5+ years of experience working in static timing analysis, DFT, physical design or CAD
  • Static Timing Analysis with Primetime, Tempus, or equivalent
  • Solid Perl, Python and/or Tcl coding/debug skills coupled with an understanding of the design challenges in advanced technology nodes
  • Fundamentals of statistics, hypothesis testing, data mining, Machine Learning and Design of Experiments.
  • Prior exposure to DFT, Tetramax, silicon debug, or semiconductor processing is a definite plus.

Description
- Work with design teams, DFT, CAD, and product engineering to design experiments, analyze results and refine design methodologies
- Data mining and analysis of silicon data to establish correlation metrics to design closure activities including Static Timing Analysis
- Assist in developing and deploying design closure margins and methodologies targeted to optimize power/performance tradeoffs which have material impact on the final products

Education & Experience

PhD, MS or BS degree in a related technical discipline.

Additional Requirements

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Sr. CAD Engineer, Silicon Learning and Static Timing Analysis

Apple, Inc.
Cupertino, CA 95014

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