Sr. CAD Engineer– Design Verification Methodology

Portland, OR
  • Job Code

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices.

As a member of our CAD team, you will develop, maintain, and improve existing sophisticated software systems for regression-testing Apple's silicon designs in software simulation, to find and report defects in our chip designs, and thus ensure that Apple tapes-out world-class silicon. Your experience and innovative ideas will inform the design of the next generation of these regression systems. Your insight, your skill at diagnosing the root cause of complex problems, and your ability to guide engineers who come to you with problems will be important contributions to an extended CAD team that comprehensively supports Apple's DV and chip design engineering efforts. You will work closely with EDA vendors to incorporate new capabilities of their commercial tools, and to resolve problems

Key Qualifications

  • You should have the following qualifications:
  • At least 10+ years of relevant experience with MSEE/CE/CS
  • Fluent in Verilog and SystemVerilog; familiarity with VHDL a plus
  • Very experienced working with Synopsys VCS, Xcelium, Incisive or Modelsim
  • Strong scripting abilities in PERL needed; TCL or Python is preferred
  • Strong communications skills and prior customer support experience is a positive
  • Experience writing or maintaining the script or Makefile that builds the simulation program from RTL is a plus
  • Familiarity with Verdi, Indago and/or SimVision is considered a plus
  • Knowledge of C and C++ is a plus


In this exciting role, your responsibilities will include:
- Develop, maintain, and improve an existing system for regressing RTL
- Role involves debugging vendor tool problems
- Interacting with DV team to help solve their problems
- Implement new functionality to solve emerging problems or to optimize already existing methods

Education & Experience


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Sr. CAD Engineer– Design Verification Methodology

Apple, Inc.
Portland, OR

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