SOC Validation Engineer

Intel
San Jose, CA 95113
  • Job Code
    JR0181629
Job Description

This candidate will oversee definition, design, verification, and documentation for System on a Chip (SoC) development. Determine architecture design, logic design, and system simulation. Define module interfaces/formats for simulation. Perform Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contribute to the development of multidimensional designs involving the layout of complex integrated circuits. Perform all aspects of the SoC design flow from high level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyze equipment to establish operation infrastructure, conduct experimental tests, and evaluate results. May also review vendor capability to support development.


Qualifications

Candidates must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed below would be obtained through a combination of Industry job relevant experience, internship experiences and or schoolwork/classes/research.

Education Requirement:

- Bachelor's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 6 years of industry work experience, or

- Master's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 4 years of industry work experience, or

- PhD in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 2 years of related work experience.


Minimum Qualifications:
- 4+ years of experience in relevant Pre-Silicon validation position having gone through multiple project cycles to gather in-depth experience.
- 4+ years of experience in logic design verification with various tools and methodologies including System Verilog, Perl, OVM/UVM, logic simulators, and coverage tools.
- 5+ years of experience with pre-silicon simulation tool flows such as Synopsys VCS Verdi and DVE.
- 4+ years of experience in C or UVM for developing verification test benches and constrained random verification.


Preferred Qualifications
- Experience with PCIe, DDR, Ethernet, PHY and Processors.

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.



Other Locations

US, California, Santa Clara



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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SOC Validation Engineer

Intel
San Jose, CA 95113

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