SoC Structural Design Engineer

Intel
Hudson, MA 01749
  • Job Code
    JR0189344
Job Description

In this position you will be part of the world class SOC design team within the Xeon Performance Group XPG designing the next generation Xeon SoCs/IPs for Server markets.

Your responsibilities will include but not be limited to:

  • Full Chip high speed fabrics design
  • Full chip DFT and DFD fabrics design
  • Full Chip and subfc level Timing model builds/analysis
  • Fullchip clocks and timing constraints generation/verification
  • Fullchip timing quality convergence and Full Chip Timing convergence using Synopsys Fusion/ICC tools
  • Timing verification using Synopsys PrimeTime as well as Fishtail and simulations using Synopsys/Intel tools


Behavioral Traits

  • Excellent analytical and independent/creative problem-solving skills
  • Excellent communication and leadership skills to work through several teams across multiple geographies


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences. This is an entry level position and will be compensated accordingly.

Minimum Qualifications:

  • Candidate must have a Master's/PhD in Electrical/Computer Engineering Computer Science
  • Completed Coursework in or internship work experience with Primetime OR PTECO/PrimeECO OR equivalent timing convergence tools OR Circuit/IP/SOC timing 


Preferred Qualifications:

Experience with/in:

  • Converging Fullchip level or IP level timing
  • Post silicon debug, speed push, vmin characterization and post silicon design fix
  • Circuit design and end to end RTL2GDS design convergence
  • ICCDP and Formal Equivalence
  • TCL, Perl, Python programming
  • Timing convergence in multiple internal and external to Intel process technologies
  • Timing convergence with Cadence timing verification tools

Inside this Business Group

Xeon Performance Group (XPG) delivers custom server SoC design solutions to our data center customers. It is chartered to deliver data centric silicon that is high-performing, cost-effective, high-quality, and on schedule in way that increases market share and drives the best solutions for our customers.


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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SoC Structural Design Engineer

Intel
Hudson, MA 01749

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