SOC Structural Design Engineer

Intel
Austin, TX 78701
  • Job Code
    JR0186480
Job Description

Come join Xeon the Austin Networking Silicon Solutions Structural Design (SD) team and buckle up. This is an efficient team that has demonstrated results in general market and custom contracted products. SD engineers on this team can move through all phases of synthesis, physical design, and timing/physical verification.

Block owners drive physical and timing closure for their blocks/subsystems and shuffle to help where the need is greatest (e.g. verification tasks) to gain high execution efficiency.

In this role, the responsibilities include, but are not limited to:

  • Oversees definition, design, verification, and documentation for SoC (System on a Chip) development.
  • Determines architecture design, logic design, and system simulation.
  • Defines module interfaces/formats for simulation.
  • Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs.
  • Contributes to the development of multidimensional designs involving the layout of complex integrated circuits.
  • Performs all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing.
  • Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.


Minimum Qualifications:

The candidate must have a Bachelor's degree in Electrical/Computer Engineering OR a Master's/PhD degree in Electrical/Computer Engineering and experience in:

  • Synthesis
  • APR (ICC2 or ICC_DP or related tool set)
  • Timing closure
  • UPF and multi-power domain designs
  • Structural design basics and block/FC builds
  • Standard ASIC EDA tools like ICC2, Fusion, DC, Prime Time, Star RC, RV
  • Scripting/coding skills, Unix, Bug filing systems, etc.


Preferred Qualifications:
 

  • Demonstrated results in taking a block(s) or subsystem completely through all phases of the construction and verification flow to tape-in (i.e. performance, power and verification fully converged)

Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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SOC Structural Design Engineer

Intel
Austin, TX 78701

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