SOC Structural Design Engineer

Intel
Austin, TX 78701
  • Job Code
    JR0174901
Job Description

Come join the Xeon and Networking Engineering (XNE) Physical Design Group in Austin. This is an exciting team that has demonstrated results on general market and custom contracted products. Engineers on this team will move through all phases of synthesis and physical design closure. APR owners drive physical and timing closure for their blocks or subsystems and work with cross functional teams to help out when needed. The customer projects offer real time external feedback on the value of our work. We are looking for an experienced Physical Design Engineer to jump in and start making an impact.

In this role responsibilities include although not limited to:

  • Block subsystem FC (full chip) contexts with synthesis
  • Clock distribution
  • Constraints generation and verification as well as APR Timing closure
  • Layout Verification
  • FEV (functional equivalents verification)
  • Power optimization and Power aware verification
  • Reliability Verification


In addition to the qualifications listed below the ideal candidate will also have:

  • Excellent analytical and problem solving
  • Strong verbal/written communication skills
  • Effective team player with continuous learning mindset
  • Ability to balance multiple tasks
  • Willingness to work in a fast-paced environment and have as much fun and growth as possible in the process


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

The candidate must have a Bachelor's degree in Electrical/Computer Engineering or equivalent and 4+ years of experience OR a Master's/PhD degree in Electrical/Computer Engineering or equivalent and 3+ years of experience in :

  • Synopsys, Cadence or other industry standard EDA tools
  • Synthesis
  • Timing closure
  • UPF multipower domain designs
  • Structural Design basics
  • Scripting skills such as Python, Perl or TCL


Preferred Qualifications:
 

  • Demonstrated results in taking a block or subsystem completely through all phases of the construction and verification flow to Tapein i.e. performance power and verification fully converged.

Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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SOC Structural Design Engineer

Intel
Austin, TX 78701

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