SOC/Software Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0180735
  • Jobs Rated
    8th
Job Description

Now is an exciting time for Intels Design Enablement Group! This position is within the Design Enablement (DE) organization of Technology Development (TD). At Intel, Design Enablement is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies and partner with Technology Development to deliver cost-effective, competitive design platform.

We are hiring in Hillsboro OR, Santa Clara CA, Phoenix AZ, and Folsom CA

In this position you will help us with at least one of the following responsibilities:

  • Standard Cell Library
    • Standard cell library definition, circuit implementation, layout architecture, design rule closure, optimization for performance and robustness, modeling, and characterization.

  • Power-Performance-Area Optimization
    • Optimize block Power-Performance-Area (PPA) with emphasis on synthesis, place, and route on latest internal/external core/graphics/soc designs
    • Work with Technology Process team to co-define next generation technology node to push Moore's law to the next level
    • Provide standard-cell architecture feedback to the library team through block PPA
    • Explore memory options for next technology nodes and provide block PPA impact
    • Co-optimize Tools & Flow Methodology (TFM) with EDA tool vendors to improve PPA and deliver world-class technology node offerings
    • Work closely with product teams to provide block PPA guidance and TFM recommendations

  • Software Engineering
    • Develop in-house physical design machine learning capability to explore design solution space, improve block PPA, and guide process technology optimization
    • Develop software to automate layout and/or schematic generation for library collaterals
    • Develop validation tools/flows
    • Develop software for data analysis on library development and validation
    • Develop parameterized cells (PCells/PyCells)
    • Collaborate with and provide layout feedback to designers and process engineers
    • Provide technical support to users

  • SOC Design
    • Realize block PPA designs on silicon through test-chips

Behavioral traits that we are looking for:

  • Written and verbal communication skills
  • Teamwork, problem-solving, and data analysis
  • Ability to work across geographical locations

By applying to this posting, youll be considered for multiple roles within Design Enablement (DE)

This is an entry level position and will be compensated accordingly.



Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.

Minimum skills and experience that will get you noticed:

  • Candidate must possess a Masters or Ph.D degree in Electrical Engineering, Electronics Computer Engineering, Computer Science, Computer Engineering, or a related discipline
  • Digital, mixed-signal, memory, and/or analog CMOS circuit design for low-power and high-speed VLSI
  • Experience in semiconductor device physics and scaling

Preferred experience in one of the following areas:

  • SoC/IP Physical design
    • Floorplan optimization for block Power
    • Logic Synthesis, Place & Route, Static Timing
    • Timing budgeting and analysis
    • Power grid design and IR analysis
  • Software
    • Proficient with UNIX/Linux computing platform
    • Software development/programming in high-level languages (e.g., Java, C++, TCL, Lisp, Scheme, Perl) 
    • Artificial Intelligence, Machine Learning (AI/ML)
    • Experience with CAD tools from Cadence, (Virtuoso, Spectre and its scripting language SKILL), Synopsys (Custom Designer, Hspice, Star-RC, IC Validator) and Mentor (Calibre)
    • Technology design rules, process development, and process integration 
    • PDK/P-Cell development
    • Analog design

By applying to this posting your resume and profile will become visible to Intel Recruiters / Sourcers and will allow them to consider you for current and future job openings aligned with the skills and positions mentioned above.

#designenablement
@designenablemnt
#LI-JR1 

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth



Other Locations
US, Oregon, Hillsboro; US, California, Folsom; US, Arizona, Phoenix; US, Texas, Austin;



Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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SOC/Software Engineer

Intel
Santa Clara, CA 95050

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Software Engineer
8th2017 - Software Engineer
Overall Rating: 8/199
Median Salary: $100,690

Work Environment
Good
53/199
Stress
Very Low
24/199
Growth
Very Good
32/199