SoC Reset Clock Fuse (RCF) Architect

Intel
Hillsboro, OR 97123
  • Job Code
    JR0179025
  • Jobs Rated
    187th
Job Description

The Intel Power Architecture and Technologies (IPAT) group is looking for a SoC Architect within the Reset - Clock - Fuse plus Firmware Load (RCF) Architecture team.

The qualified candidate will be part of the architecture team defining the next generation state-of-the-art DataCenter product for Reset, Clock plus Fuse architecture. Within Intel's product lines the extreme high scale processor and multiple dies on package for disaggregated processors requires highly innovated solutions in Reset Architecture, Clock Architecture, and Boot-time Configuration plus Firmware Loading. Customer visible values can be added at Performance and Power optimization, in-field uptime, customer elected functionalities, product quality assurance through manufacturing test effectiveness, etc.

In this position you will help the team that defines interfaces between hardware, firmware, and software. Defines IP standards for rapid and seamless assembly into the SoC. Analyze existing algorithms and implementations for defects and weaknesses and proposes changes to improve function and performance. Use knowledge and experience to influence architecture and design for future products.

In this role, responsibilities include (but not limited to):

  • Determines, specifies, and evaluates the viability of complex hardware features and structures and ensures that software and hardware designs interface correctly.
  • Designs framework for functions. Defines, documents and tests processes for inclusion into technical platforms, subsystem specifications, input/output and working parameters for hardware and/or software compatibility.
  • Identifies, analyzes, and resolves subsystem and/or SoC design weaknesses.
  • Influences the shaping of future products by significantly contributing to the architecture used across design families.
  • Provides multilayered technical expertise for next generation initiatives.
  • Behavioral traits that we are looking for:
  • Strong communication skills both written and verbal.
  • Strong attention to technical detail, problem solving skills and tolerance to ambiguity
  • Ability to Multi-task and ability to Work in a Dynamic Team-Oriented Environment
  • Possess strong teamwork, problem-solving and influencing skills


Qualifications

Minimum Skills required:


Must have Bachelor's degree in Electrical/Computer Engineering, Computer Science or related field with 4+ years of relevant experience. OR a Master's degree in Electrical/Computer Engineering, Computer Science or related field with 2+ years of relevant experience:

Your experience should be in the following:

  • Microprocessor or ASIC fundamental development life cycle
  • IA-32 architecture/micro-architecture, or computer system architecture
  • Hardware/software interfaces, interactions, or debug
  • Experience in RTL-level Logic Design and Validation
  • Presentation and documentation experience in at least at least some of MS Word, MS PowerPoint, MS Excel, MS Visio, PlantUML, Wavedrom, MS Teams, etc.

Preferred skills that will make you stand out:

  • Post-silicon debug experience, especially familiarity with High Volume Manufacturing (HVM) setup flows and test platform constraints.
  • Pre-silicon validation and/or testing, especially within processor design teams
  • Platform architecture for fundamentals of board, components, interconnect, packaging.
  • Operating system knowledge
  • CPU power management
  • UNIX command-line tools
  • Low-level software or firmware programming skills in assembly or C
  • Software programming languages: C or C++
  • Other software or scripting programming languages: Ruby, Python, or Perl

Inside this Business Group

The Design Engineering Group is a worldwide team responsible for the design, development, validation, and manufacturing of IPs and SOCs. Our mission is to deliver leadership products through groundbreaking innovations.



Other Locations

US, California, Folsom;US, California, Santa Clara;US, Massachusetts, Hudson;US, Texas, Austin



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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SoC Reset Clock Fuse (RCF) Architect

Intel
Hillsboro, OR 97123

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Architect
187th2019 - Architect
Overall Rating: 187/199
Median Salary: $79,380

Work Environment
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190/220
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183/220