SOC Network on Chip Physical Design/Timing Convergence Specialist

Hillsboro, OR 97123
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Job Description

Looking for an SOC Global Design Engineer, that is well versed in timing convergence and programming to join a Senior Server-class Integration Convergence team. The charter of the sub-team is to drive the specification, development, and convergence of SOC interconnect fabrics and global components necessary to meet the performance, functionality, and DFT DFM requirements. The team also has a hand in IP coordination and integration and planning design convergence methodology and work model optimization for efficiency and productivity continuous improvement.


In this position, your responsibilities will include, but not be limited to:

  • Specification design simulation and verification of SOC high speed interconnect network on chip
  • Working with IP providers on electrical and layout optimization to balance area and frequency specifications
  • Working with clocking team to balance skew/power to meet interconnect speed requirements
  • Working with architecture team to translate performance requirements into latency and frequency specifications for implementation
  • Participating in the advancement of timing convergence technology and work model
  • Advancing the state of the art in top-level global fabrics implementation, constantly improving layout and timing convergence KPIs each generation
  • optional participation in post-Si timing debug and correlation


The ideal candidate should exhibit the following behavioral traits:

  • Strong verbal and written communication skills
  • Strong teamwork skills and mentality
  • Capability of managing a high intensity dynamic work environment
  • Excellent interpersonal skills for interaction with internal and external IP and tool vendors


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

Must have Bachelors degree in Electrical Computer Engineering, Computer Science, or related field with 4+ years of relevant experience. OR a Masters degree in Electrical Computer Engineering, Computer Science, or related field with 3+ years of relevant experience. OR a PhD degree in Electrical Computer Engineering Computer Science or related field with 1+ years of experience.


Your experience must include the following:

  • Experience with tight technical team interactions for technological advancement and facilitation of stringent timing clocking convergence goals
  • Strong familiarity with processor design and convergence
  • Strong familiarity with static timing analysis concepts
  • Familiarity of layout and extraction issues associated with leading edge processes
  • Familiarity with clock distribution theory approaches/issues
  • Strong programming and automation development skills - Perl and/or C++ and Tcl/Tk Preferred


Preferred Qualifications:

  • Familiarity with Prime Time, Fusion Compiler, ICC, Cadence Innovus
  • Good customer support and collaboration skills spanning multiple design sites

Inside this Business Group

Xeon Performance Group (XPG) delivers custom server SoC design solutions to our data center customers. It is chartered to deliver data centric silicon that is high-performing, cost-effective, high-quality, and on schedule in way that increases market share and drives the best solutions for our customers.

Other Locations

US, California, Santa Clara

Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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SOC Network on Chip Physical Design/Timing Convergence Specialist

Hillsboro, OR 97123

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19th2019 - Physicist
Overall Rating: 19/199
Median Salary: $117,220

Work Environment
Very Good