SoC Engineering Manager

Folsom, CA 95630
  • Job Code
Job Description

We are seeking an experienced and dynamic Post-Silicon Engineering Manager for Intel's IP Engineering Group (IPG) which is part of the Design Engineering Group (DEG). IPG's Test Chip Engineering team is chartered with transforming Intel and DEG/IPG with silicon-proven test-chips for leading-edge IPs and technologies. This leader will drive post-Silicon development activities of Test Chips for PPA/Technology co-optimization, Foundational IPs, Complex IP Sub-systems in support of IP and Technology certification ahead of product intercept for internal IPG customers as well as support external customers in partnership with Intel Foundry Services (IFS). Responsibility includes close collaboration with IP and post-Silicon teams in Intel Validation Engineering and Manufacturing Product Engineering to define test strategy, success criteria, test plans and oversee post-Silicon bring-up and execution to ensure test-chips are meeting IP specifications and landing zone requirements. This leader will report directly to the Test Chip Group General Manager in the IP Engineering Group (IPG).

The position requires strong analytical, project management, and business partnering/influencing skills. The candidate must have experience driving cross-organizational issues and projects to resolution, excellent written and communications skills, and a good understanding of Intel's highly complex products, technologies, and business strategies. The position requires strong business and technical acumen, disciplined process management, problem-solving skills, multitasking ability, and attention to quality and detail. The job is in a fast-paced environment and requires a dynamic individual to succeed. The candidate must be results-oriented, capable of synthesizing and abstracting complex information into clear messages. The position requires understanding the needs of our IP design partners and mobilizing the organization to address those needs with urgency and customer obsession. Working with cross-organizational stakeholders to solve engineering problems unique for our customers.

Responsibilities will include:
Leading global/matrixed team of IP and Post-Silicon stakeholders to deliver test-chip post-Silicon programs
Partner with IPG IP team and MPE/IVE on post-Silicon development and ensure that IPG IPs coverage requirements are met by FV/EV/PPV
Engage with DEG IP and Post-Silicon leaders to drive transformation for Test Chip strategy and post-Silicon debug/validation methods.
Drive retrospectives and continuous improvements.


Minimum 10+ years of experience leading engineering teams to deliver complex IP/SoC post-Silicon programs.
Minimum of 10+ years of experience in leading global teams.
MS in Electrical Engineering, Computer Science or semiconductor related majors preferred
Knowledge of validating Foundational IPs and Complex Analog Mixed-Signal IPs, HSIO, Memory Sub-system required
Deep hands-on knowledge of IP post-silicon validation and debug methods
A combination of business acumen, organization savvy, networking capabilities, and expertise to get results across multiple groups and disciplines
Strong self-initiative and persistence, ability to deal with a high degree of ambiguity and drive clarity in key areas
Detail orientation and ability to gather, analyze and interpret data to drive results
Strong communication and presentation skills and ability to handle high degrees of task and deadline pressure

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, Arizona, Phoenix;US, California, Santa Clara

Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter....

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SoC Engineering Manager

Folsom, CA 95630

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