SOC DFT engineer

Intel
Austin, TX 78701
  • Job Code
    JR0199370
Job Description

The Xeon & Networking Engineering Group (XNE) is focused on developing and delivering networking and 5G products for the data center roadmap.

In this role responsibilities include, although not limited to:

  • Develops and supports design for test (DFT) structures.

  • Determines design for test approaches and develops DFT architecture.

  • Designs and verifies DFT structures for memories (MBIST), digital and analog circuitry.

  • Performs scan synthesis.

  • Creates, simulates and verifies automatic generated test patterns (ATPG)Creates functional tests and corresponding test patterns.

  • Knows about failure mechanisms in silicon production and creates test algorithms.

  • Supports silicon bring up of test patterns.

  • Performs diagnosis of test patterns on silicon and optimizes test time.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

The candidate must have a BS and 3+ years of experience OR a MS in Electrical and/or Computer Engineering and 2+ years of experience in the below:

  • SoC Design-For-Test (DFT) principles including SCAN for logic testing, BIST and repair for memory test, IEEE1149 JTAG Boundary SCAN. IEEE1687 IJTAG

  • RLT integration methodologies - IP DFT integration

  • DFT architecture development and validation methodologies at SoC

  • Test insertion, test pattern generation, simulation, and validation

  • Intel DFT methodologies - Taplink, STF, USC/ULT, DFTbuild, ITPP

  • Scripting Languages, e.g., PERL, Tcl/Tk.


Preferred Qualifications:

  • Knowledge of manufacturing tester capabilities. Automatic test equipment (ATE), and test program experience.

  • Industry-standard DFT tools such as Mentor Tessent DFT, Synopsys DFT Compiler.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intels products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moores Law and groundbreaking innovations.  DEG is Intels engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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SOC DFT engineer

Intel
Austin, TX 78701

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