SOC Design Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0165528
Job Description

This position is part of the development team that will be providing IP components for server class CPUs. The team is responsible for development and documentation of multiple generations of IPs connecting the coherent CPU fabric to the IO agents

Responsibilities includes but not limited to:

  • Participation and support in the development of next generation IP components with an emphasis on IO flows connecting PCIe and the coherent CPU fabric.
  • The expectation is to have an efficient relationship with the validation team providing timely bug fixes with physical design team members to support SIP qualification for meeting timing goals and with post silicon teams to help debug and resolve issues encountered during product qualification.
  • Candidate will work with architecture teams to define and design next generation features to support IO agent flow
  • Extensive knowledge in RTL design concepts power efficiency synthesis timing and verification flows
  • Excellent problem solving capabilities and debug skills along with customer skills

The ideal candidate would be disciplined motivated and innovative with a focus on quality

  • Good understanding of database issues for large multisite design projects
  • The successful candidate must be customer oriented and exhibit informed risk taking skills
  • The candidate will be expected to work under minimal supervision and maximum flexibility to meet project deadlines
  • Good written and verbal communication skills
  • Must be a self starter with good initiative to seek and explore multiple alternatives


Qualifications

You must possess the below minimum qualifications to be initially considered for this position Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Candidate will have a Bachelor's degree in Electrical or Computer Engineering or equivalent with 10+ years of experience in - OR- Master's degree in Electrical or Computer Engineering or equivalent with 7+ years of experience in:

  • VLSI or ASIC design and have a solid understanding of front and back end CAD tool flows
  • System Verilog or other RTL knowledge

Additional Preferred Qualifications:

  • Candidate will have experience with development and documentation of multiple generations of IPs connecting the coherent CPU fabric to the IO agents
  • Hands on experience in VLSI ASICIC design flows and methodologies
  • Technical understanding of industry standard IC CAD tools like Synopsys DC ICC Design and Timing verification
  • Good understanding of physical design challenges required for highly integrated high performance IC designs

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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SOC Design Engineer

Intel
Santa Clara, CA 95050

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