SOC Design Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0171336
Job Description

This role involves a blend of physical design kit (PDK) and physical design verification (PDV) methodology development. The role also involves consulting in physical implementation and support products in new technology nodes.

In this role responsibilities include, although not limited to:

  • Contribute to development and deployment of physical design kit (PDK) to support MXS IP development,
  • Contribute to development and deployment of physical design verification (PDV) methodology and tools, including working with foundry partners in DRC run sets development and/or optimization
  • Work with internal IP/design implementation teams and external customers in physical design and verification aspects
  • Lead the continuous improvement of the PDK/PDV methodology for existing nodes and help define/develop flow for new technology nodes
  • Work with 3rd party EDA vendors, Foundries and internal IP teams to resolve issues and drive improvements in vendor tools / IP deliverables.

The ideal candidate should exhibit the following behavioral traits:

  • Effective presentation and communication skills (written and oral)
  • Strong problem solving skills and an ability to think outside the box
  • Ability to work / lead effectively in cross functional teams / multiple geographies and mentor junior engineers when needed.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

The candidate must have a Bachelors degree in Electrical/Computer Engineering or Computer Science and 6+ years of experience -OR- a Masters degree in Electrical/Computer Engineering or Computer Science and 4+ years of experience in:

  • Strong understanding of PDK development, DRC/LVS toolkits, and ASIC design flow in Cadence or Synopsys tool environments.
  • Prior PDV methodology development, MXS PDK development, EDA vendor/Foundry interaction or exposure to technology nodes 10nm and below is a plus.

Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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SOC Design Engineer

Intel
Santa Clara, CA 95050

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