SoC Design Engineer

Intel
San Jose, CA 95113
  • Job Code
    JR0196354
Job Description

Full chip integration lead with RTL experience. Job will involve working with the IP teams to put the chip together. Support cross-functional teams as your customer. Willing to participate in chip definition and full chip specification. Willing to lead junior engineers. Excellent communication and collaboration skills.


    Qualifications

    Minimum Education Qualifications

    • Bachelor's degree in Electrical Engineering with 5 years of experience

    Minimum Required Qualifications

    • 5+ years of experience using Verilog or VHDL, Synopsys Design Compiler, PrimeTime, and scripting tools (Python, Tcl, and etc)
    • 3+ years of ASIC design flow experience, from floor-planning, RTL design/synthesis, to static timing analysis

    Additional Preferred Qualifications

    • Master's Degree or higher.
    • Experience reading and understanding schematic and SoC/ASIC/FPGA RTL designs.
    • Experience in FPGA design flow synthesis, place route

    Inside this Business Group

    The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.



    Other Locations

    US, Oregon, Hillsboro;US, Texas, Austin


    Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



    Posting Statement

    All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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    SoC Design Engineer

    Intel
    San Jose, CA 95113

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