SOC Design Engineer - Physical Clock Design

Intel
Hillsboro, OR 97123
  • Job Code
    JR0197487
Job Description

Come join Intel's Design Engineering Group, responsible for designing Client SoCs that make up more than half of Intel's annual revenue. We envision the future of computing and design for the next generation of laptops and desktop computers.

We are looking for an SoC (System on Chip) Physical Clock Design Engineer, ready to research, design, develop, and test lead Intel designs as we reimagine how to build SoCs at Intel and in the semiconductor industry. This role is within Intel's highly regarded Devices Development Group headquartered in Portland, Oregon with additional sites in Austin, Texas and Penang, Malaysia. Our bold purpose as a company is to 'create world changing technology that enriches the lives of every person on earth', and this role is instrumental in furthering our mission to shape the future of technology.

Your responsibilities may include but not be limited to:

  • Design for global clock IP blocks
  • Debugging layout, extraction, and simulation issues
  • Physical design and synthesis flows
  • Writing checkers to validate the physical design


The ideal candidate will demonstrate the following skills in addition to the qualifications listed below:

  • High motivation and results orientation
  • Strong problem solving skills
  • Excellent interpersonal skills, including written and verbal communication
  • Teamwork, negotiation, and presentation skills
  • Willing and able to mentor junior engineers


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Education requirement

Bachelor's or Master's degree in Electrical or Computer Engineering or a related field.


Minimum Qualifications
5 years of experience with clock design.
4 years of experience with extraction and simulation tools.
4 years of experience with physical design and synthesis flows.
2 years of experience with Formal Equivalence Verification (FEV).
2 years of experience with a scripting language, such as TCL, Perl, or Python.

Preferred Qualifications
Experience with Synopsys icc2 tool.
Experience with global and/or high speed clock design.
Experience with Primetime simulation.
Experience with clock architecture.
Experience with standard cell libraries, including cell naming and characterization.
Experience with Formal.
Experience with multiple power domain analysis, using standard Power Formats UPF or CPF.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intels products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moores Law and groundbreaking innovations.  DEG is Intels engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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SOC Design Engineer - Physical Clock Design

Intel
Hillsboro, OR 97123

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