Soc Design Engineer

Intel
Phoenix, AZ 85003
  • Job Code
    JR0195845
Job Description

The Customer ASIC (Application Specific Integrated Circuit) DPS (Design Productivity and Solutions) Solutions team in PSG (Programmable Solutions Group) is responsible for developing cutting edge SoC/ASIC Design System.  Activities include enabling RTL, synthesize, place, route, and perform static timing and run verification tools to complete the design to tape-out. The team has been responsible for supporting multiple execution teams to tape-out by providing solutions that helps converge the physical design at a faster than industry standard pace. 

The Soc Design Engineer will be responsible for, but not limited to:

  • Working with the broader design team to gather specifications for the target designs and help configure the Design System to satisfy the needs.  

  • Delivering fine-tuned DS for rich and timely execution of projects. 

  • Performing block/full chip implementation and/or verification execution on ASIC projects.  

  • Leading and Mentoring Junior Engineers in specific Physical Design domains such as Static Timing Analysis and Auto Place and Route.

  • Driving technical activities of physical design during all phases of DS development and Execution.

  • Static Timing Analysis (STA) (Block and full chip)

  • SoC Design Integration Methodology

  • Performing optimization including co-optimization work with process teams to create Best in Class Design System.

  • Physical Implementation using Synopsys and/or Cadence Tools

  • Analyzing Multiple Power Domain using UPF/CPF

  • VLSI Design Automation / Data Structures and Algorithms

  • Scripting skills using Python/Perl/TCL

The ideal candidate will have the following attribute in addition to the qualifications listed below:

Effectively communicating with large numbers of design engineers providing high quality documentation and presentations.


Qualifications

You must possess the minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Relevant experience can be obtained through schoolwork classes and project work, internships, military training, and/or work experience.

Required Education:
The candidate must possess a Bachelor's or Master's degree in Electrical or Computer Engineering or a related field.

Minimum Qualifications:
4+ years of experience in the application of methodologies and physical design and automation for SOC, Static Timing Analysis and APR, Floor planning and routing, physical design convergence, and tape in.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Soc Design Engineer

Intel
Phoenix, AZ 85003

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