SoC Design Engineer

Intel
Hillsboro, OR 97123
  • Job Code
    JR0195408
Job Description

The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower peoples digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver IP solutions for products that impact customers lives? If so, Come join us to do something wonderful.

The Compute Express Link (CXL) Cache Mem IP team (IPG) is looking for a passionate logic Engineer with background in front end design automation and tools.

This position provides a unique opportunity to mix and grow with multiple responsibility of micro-architecture development, RTL coding and tools/flows. The candidate will be part of a silicon design team chartered with developing and delivering multiple generations of state of the art, highly configurable upstream and downstream Compute Express Link (CXL) cache and Mem IPs to multiple Intel server SOCs and IFS.

Responsibilities will include but not limited to:

  • Feature evaluations for complexity and effort for new features, develop microarchitecture and write RTL code. Own feature execution, fix all quality issues and help in SIP qualification.
  • Enhance quality check methodologies for pre-silicon development of IP. Bring creative initiatives to improve efficiency and velocity of the team.
  • Interact and work closely with architecture, design team members, SIP qual team, validation team and SoC stakeholders
  • Work with partner organizations / internal team to enable tool automation flows to enhance team productivity.
  • Pilot / Test / Enable newer tool flows, write scripts in Perl/Python for autogenerate RTL from specification

The role requires the following attributes / qualifications:

  • Should have excellent problem solving skills, written and verbal communication.
  • Hands-on RTL coding and micro-architecture development using System Verilog.
  • Background in tools and design automation flows like model builds, and other quality checks etc.
  • Ability to work in a dynamic environment, ability to understand abstract concepts and multitask.


Qualifications

This position requires meeting the below minimum qualifications to be initially considered. Preferred qualifications are in addition to the minimum requirements and are considered a major plus.

Minimum Qualifications:

Candidate must have a Bachelor's degree in Electrical/Computer engineering with 4+ years' experience -OR- a Master's degree in Electrical/Computer engineering with 3+ years' experience in:

  • VLSI design
  • Reading and interpreting technical specs and write Register Transfer Level (RTL) code in system Verilog.
  • Quality checks tools and front end design automation flows. Experience in scripting with Perl/Python
  • Feature evaluations for complexity and effort

Preferred Qualifications: Experience in:

  • Computer architecture and coherency protocols
  • Digital PHY and high speed IOs
  • Supporting post-silicon bring up and debug.
  • Formal verification and assertion based verification

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.



Other Locations

US, Arizona, Phoenix;US, California, Santa Clara;US, Texas, Austin


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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SoC Design Engineer

Intel
Hillsboro, OR 97123

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