SoC Design Engineer

Intel
Hillsboro, OR 97123
  • Job Code
    JR0188632
Job Description

The Full-Chip Integration team is looking for an SoC Design Engineer to join Design Enablement (DE) team in Technology Development Organization (TD). The charter of the team is to develop physical design methodology for Test Chip lead vehicles which are primarily used for Intel's next generation process development and high-volume certification.

The specific role focuses in the layout domain and encompasses engagement with manufacturing on cutting-edge process nodes, facilitation of hierarchical layout convergence and correct-by-construction assembly, IP integration oversight, driving and qualification of design to meet tape-in requirements, and delivery of SOC design to manufacturing.

As a SoC Design Engineer, your responsibilities will include but not be limited to:

  • Developing layout design methodology and productivity automation for cutting edge process nodes

  • Working closely with LTD Process Engineers to define critical Design features that needs to be exercised in the early lead vehicle test chips.

  • Establishing, orchestrating, overseeing, and maintaining hierarchical layout design specifications for correct-by-construction integration

  • Building and executing tactical plans to converge hierarchical SOC layout design against aggressive schedule requirements

  • Orchestrating mock full-chip assembly and tape-ins in preparation for the real thing and to provide package and tape-out partners with representative data for planning and product prep

  • Building and supporting tools, capabilities, methods, and work models for global layout design and convergence

  • Driving all aspects of physical design convergence, including preparing layout hierarchy for design tape-in, debugging and resolving issues uncovered by verification tools

  • Working with tool/flow owners and vendors for ongoing tool/methodology improvement

  • Working closely with Engineering, DAs, and manufacturing partners with a goal to robustly tape-in a complex multi-hierarchical SOC within hours of final block completion

The ideal candidate should exhibit the following behavioral traits:

  • Verbal and written communication skills

  • Ability to work well both autonomously and in an intensive, cooperative team environment

  • Exhibiting strong interest in Layout design Motivation to continuously learn and drive to push improved layout productivity and efficiency

This is an entry level position and compensation will be given accordingly.


Qualifications

You must possess minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.

 

Minimum Qualifications:

 Master's degree in EE or ECE, with 6+ months experience in the following areas:

  • Cadence (Virtuoso Layout)
  • Layout design
  • Design rules check (DRC) and Layout vs Schematic (LVS)
  • Perl or Python or Tcl
  • Floorplanning

 

 

Preferred Qualifications:

  • Comprehension of electrical behavior of materials and insight into ways to improve reliability and manufacturability
  • Floor planning with ICC2-DP and ability to customize the flow based on design needs.
  • Exposure to Runset development using ICV/Calibre to facilitate automation to improve layout productivity
  • Knowledge on device physics
  • Project Management skills on coordinating and tracking the entire design cycle of a project from Feature definition to final Tape-in

#designenablement

@designenablemnt

#LI-JR1

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Before you go...

Our free job seeker tools include alerts for new jobs, saving your favorites, optimized job matching, and more! Just enter your email below.

Share this job:

SoC Design Engineer

Intel
Hillsboro, OR 97123

Join us to start saving your Favorite Jobs!

Sign In Create Account