SOC Design Engineer

Intel
Hillsboro, OR 97123
  • Job Code
    JR0162400
Job Description

About the team:

Youll be part of Advanced Design (AD) within Design Enablement organization (DE). The team works in close collaboration with our partners in process technology and design teams spanning CPU, Graphics, Networking, and Servers. The primary focus of the team is to accurately predict the impact of process changes on density scaling and power, performance metrics thereby facilitating quick data-based decisions for scaling and power, performance commits going from one tech node to the next.

About the role:

You will be working as part of a team supporting RTL synthesis and place and route experiments using internal and external vendor tools to improve Intel's product Power, Performance, and Area, for existing and future process nodes on internal Intel Architecture (IA/X86) and external ARM IP's. You will be specifically expected to deal with changes to floorplan, corresponding scaling and its impact to power, performance, debug scaling and timing issues for the present tech node and predict how it would impact scaling, timing, and power for the next tech node, improve cell utilization and transistor density metrics and keep pushing the power, performance envelope through critical path analysis, metal layer usage by the tool, etc.


Qualifications

You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.

 

Minimum Qualifications:

Master Science in Electrical Engineering, Computer Engineering with 2+ years of industry experience OR PhD in Electrical Engineering, Computer Engineering.

Experience in the following areas:

  • Experience with: Python, Perl, TCL, Shell scripting
  • Use of industry standard placement and routing CAD tools

Preferred:

  • Floor planning and power grid setup, Clocking methodologies, IR droop and SI mitigation strategies, power and timing signoff conditions, and leveraging the industry standard tools, flows, and methodology to get the correct PPA tradeoffs.
  • Background in Artificial Intelligence and Machine Learning (AI-ML) will be a plus

#designenablement
@designenablemnt
#LI-JR1

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth



Other Locations

US, Arizona, Phoenix;US, California, Folsom;US, California, Santa Clara



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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SOC Design Engineer

Intel
Hillsboro, OR 97123

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