SOC Design Engineer

Hillsboro, OR 97123
  • Job Code
Job Description

About the team:

You will be part of Advanced Design (AD) within Design Enablement organization (DE). The team works in close collaboration with our partners in process technology, internal design teams, and external foundry customers, spanning CPU Graphics Networking and Servers. The primary focus of the team is to accurately predict the impact of process changes on density scaling and power performance metrics thereby facilitating quick databased decisions for scaling and power performance commits going from one tech node to the next.

About the role:

You will be working as part of a team supporting RTL synthesis and place and route experiments using internal and external vendor tools to improve Intels product Power Performance and Area for existing and future process nodes on internal Intel Architecture X86 and external ARM IPs. You will be specifically expected to deal with changes to floorplan corresponding scaling and its impact to power performance debug scaling and timing issues for the present tech node and predict how it would impact scaling timing and power for the next tech node improve cell utilization and transistor density metrics and keep pushing the power performance envelope through critical path analysis metal layer usage by the tool etc.


You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.


Minimum Qualifications

BS (with 4+ years of semiconductor industry experience) OR MS (with 3+ years of semiconductor industry experience) OR PhD in Electrical Engineering, Computer Engineering, or related field. 

Experience in the following areas:

  • Experience with Python Perl TCL Shell scripting
  • Use of industry standard placement and routing CAD tools
  • Floor planning, power grid setup, Clocking methodologies (CTS, MSCTS etc.)


  • IR droop, Electromigration (EM) and Reliability Verification (RV) and Signal Integrity and Crosstalk mitigation strategies power and timing signoff conditions and leveraging the industry standard tools flows and methodology to get the correct PPA tradeoffs
  • Application of Artificial Intelligence and Machine Learning (AIML) concepts to solving critical problems in the auto place and route domain


Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth

Other Locations

US, Arizona, Phoenix;US, California, Folsom;US, California, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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SOC Design Engineer

Hillsboro, OR 97123

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