SOC Design Engineer

Intel
Folsom, CA 95630
  • Job Code
    JR0188739
Job Description

Our High Speed IO group within IP Engineering Group (IPG) is looking for a Digital Design Engineer to play a critical role in DDR IO designs of next generation DDR PHYs.

You will be part of a Dynamic Design team that is developing high speed DDR IO.

As a Digital Design Engineer you will be working on multiple IPs in various stages of development ranging from RTL design to DFX enhancement and static timing analysis while interacting with Design/DFX Architects. Validation experts and SD owners.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

The candidate must have a Bachelors degree in Electrical/Computer Engineering, Computer Science or a related field with 3+ years of experience -OR- a Masters degree in Electrical/Computer Engineering or Computer Science and 2+ years of industry experience in the following:

  • RTL Design
  • Verilog HDL
  • Static timing analysis

Preferred Qualifications:

  • Some background in validation OVM and Test bench development UPF and low power design
  • DFx and Test pattern generation
  • Clock Domain crossing

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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SOC Design Engineer

Intel
Folsom, CA 95630

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