SoC Design Engineer - Block PPA

Intel
Hillsboro, OR 97123
  • Job Code
    JR0178207
Job Description

Join Intel-and build a better tomorrow. Intel is in the midst of an exciting transformation, with a vision to create and extend computing technology to connect and enrich the lives of every person on Earth. So join us-and help us create the next generation of technologies that will shape the future for decades to come

This position is within the Design Enablement (DE) organization of Technology Development (TD). At Intel, Design Enablement is one of the key pillars enabling Intel to deliver winning products in the marketplace.

Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies. As part of the Design Enablement, you will join a highly motivated team of top-notch engineers solving challenging technical problems.

AD-LT Block PPA team is looking for talented and inspired individuals to bring innovations to Intel technology offering.

The candidate should exhibit the following behavioral traits:

  • Strong physical design background

  • Problem-solving capability

In this team, you will own and participate in the following:

  • Perform block PPA with emphasized on synthesis, place, and route on latest internal/external core/graphics/soc designs and target for ambitious power, performance, and area

  • Work with process team to co-define next generation technology node from ground up and push Moore's law to next level

  • Explore standard-cell architectures together with library team and provide guidance to library optimization and choice through block PPA

  • Explore memory options for next technology nodes and provide block PPA impact

  • Co-optimize TFM with EDA tool venders (primary Synopsys and Cadence) to boost block PPA and deliver world-class process offering

  • Develop in-house physical design machine learning capability to explore design solution space and push block PPA as well as provide guidance to process technology optimization direction

  • Work intensively with product teams to provide block PPA guidance as well as TFM recommendations

  • Design delivery: Bring designs from block PPA and realize in silicon through test-chip and demonstrate world leading silicon

We're constantly working on making a more connected and intelligent future, and we need your help. Change tomorrow. Start today.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevant previous job and/or internship experience.

Minimum Qualifications

  • Possess a Master's degree in Electrical Engineering, Electronics Computer Engineering or Computer Science with 2+ years experience in the field or Ph.D. in Electrical Engineering, Electronics Computer Engineering or Computer Science

  • 2+ years experience in the following areas:

    • SoC/IP Physical design

    • Timing budgeting and analysis

    • Floorplan optimization for block Power

Preferred Qualifications:

Knowledge of:

  • Power grid design and IR analysis

  • Programming in CAD algorithm customization

  • Tape-in tape out

  • Python or TCL

  • Artificial Intelligence, Machine Learning (AI/ML)

#designenablement
@designenablemnt
#LI-JR1

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.



Other Locations

US, California, Santa Clara



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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SoC Design Engineer - Block PPA

Intel
Hillsboro, OR 97123

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