Silicon Architecture Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0176106
Job Description

Come join the Datacenter Processor Architecture Team! This is an amazing opportunity to join a highly motivated business group within Intel whose mission is to architect products that deliver leadership performance, performance efficiency and security for traditional as well as new paradigms for data centric computing in the datacenter and edge with the right balance of leadership technologies and IPs for computing, interconnect, memory and quality delivered through the best mix of silicon, packaging and platform solutions.

We are looking for a Silicon Architecture Engineer who determines, specifies and evaluates the viability of complex hardware features and structures and ensures that software and hardware designs interface correctly. Also, designs framework for particular functions.

The ideal candidate should exhibit the following behavioral skills:

            Decision-making in uncertain scenarios

            Customer oriented

            Detail orientation

            Strategic thinking


Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering or any other related field and 3+ years of work experience OR Master's degree in Electrical Engineering, Computer Science, Computer Engineering or any other related field and 2+ years of work experience
  • 3+ years of experience in driving architecture definition by balancing forward looking, competition landscape, and execution priorities.
  • 3+years of experience studying new areas, new methodology and new tool to deliver consistent improvements.
  • 3+years of experience analyzing high level product requirements and coming up with competitive solutions with holistic considerations on power/performance/area/DFT/DFD and driving architectural discussion across multiple domains and working with partners collaboratively.
  • 2+ years of experience/Familiarity with x86 uncore architecture and system architecture. Including understanding in some of the domains like: General Purpose Input/Output (GPIO), Control Register, On-chip fabric, Performance monitor, SoC/IP configuration among others.
  • 2+ years of Experience with more than one complete hardware product life cycle. Familiarity and capability to contribute to multiple stages pre-silicon and post-silicon: implementation, validation, verification, testing, and high-volume manufacturing
  • 3+ years of experience with one more programming/scripting language and able to employ it to improve daily work and guide solution for implementation issues.
  • 2+ years of experience at detail orientation in a large and complex architecture including customer and downstream consumer feedbacks and incorporating them in decision making process.

Preferred Qualifications:

  • PhD in Electrical Engineering, Computer Science, Computer Engineering or any other related field
  • Capable of navigating through uncertainty and ambiguity and providing architectural guidance to partner teams based on available data, past experience and engineering judgement.
  • Product improvement experience by setting directions and influencing partner teams for product improvement for both long term direction and immediate needs.
  • Experiencing at defining and working with overall competitive product/IP roadmap.
  • Familiarity with perimeter and interface definition at different levels: among IPs and between IP and SoC. Able to drive architecture definition considering both partition and collaboration among IPs and between IP and SoC.
  • Experience at delivering competitive products to downstream consumers and final customers.
  • Strong background and deep understanding in key domains of the team: GPIO, Control register, on-chip non-coherent fabric, performance monitor, and SoC/IP configuration.
  • Excellent technical breadth covering multiple architectural domains and different stages in product life cycle.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intels products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moores Law and groundbreaking innovations.  DEG is Intels engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.



Other Locations

US, California, Folsom;US, Colorado, Fort Collins;US, Massachusetts, Hudson;US, Oregon, Hillsboro



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Annual Salary Range for jobs which could be performed in US, Colorado:
$111,000.00-$166,390.00


Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here

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Silicon Architecture Engineer

Intel
Santa Clara, CA 95050

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