SerDes Analog Architect

Intel
Santa Clara, CA 95050
  • Job Code
    JR0181238
  • Jobs Rated
    187th
Job Description

About IFS

As an integral part of Intel's new IDM2.0 strategy, we are establishing Intel Foundry Services (IFS), a fully vertical, standalone foundry business, reporting directly to the CEO. IFS will be a world-class foundry business and major provider of US and European-based capacity to serve customers globally. Intel Foundry Services will be differentiated from other Foundry offerings with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe - available for customers globally - and a world-class IP portfolio that customers can chose from including x86 cores, graphics, media, display, AI, interconnect, fabric and other critical foundational IP, along with ARM and RISC-V ecosystem IPs. IFS will also provide access to silicon design services to help our customers seamlessly turn silicon into solutions, using industry standard design packages. This business unit is completely dedicated to the success of its customers with full P and L responsibilities. This model will ensure that our foundry customers' products will receive our utmost focus in terms of service, technology enablement and capacity commitments. IFS is already engaged with customers today starting with our existing foundry offerings and we are expanding imminently to include our most advanced technologies, which are optimized for cutting-edge performance, making them ideal for high-performance applications.

Responsibilities

  • You will deliver IP optimized for multiple Segments from High Performance Computing to Extreme low-power wireless products.
  • Define architecture, develop serial IOs in Intel cutting edge emerging technology nodes.
  • Engage with customers right from pre sales till final product as a technical contact.
  • Review customer requirements and define PPA targets for the team to deliver towards.
  • Review design results, direct and participate in post silicon debugs and characterization.


Requirements

  • Proven and exemplary record of hands on analog design of high speed PHYs - CTLE, DFE, TX, low jitter PLLs
  • Experience architecting and leading design teams to deliver serial IOs. Must have participated and led post silicon debugs and char.
  • Highly knowledgeable of serDes standards like PCIe, USB, UFS etc
  • Deep experience of cutting edge process technologies, signal integrity, packaging, board and test issues.
  • Expertise in writing Behavioral models for Analog PHYs and experience in Architecture modeling using Matlab will be a major plus.
  • Alumni of IIT/NITs/Other universities of repute preferred.
  • A great team player and must be adaptable to dynamics of a growing business.
  • Able to work with teams across the globe and able to team with customers in driving design decisions and possess good communication and presentation skills


Qualifications

  • Bachelors of Engineering in Electrical/ Electronics Engineering with 17 years experience.
  • Masters/Ph.D Preferred.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth



Other Locations

US, California, Folsom



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter....

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SerDes Analog Architect

Intel
Santa Clara, CA 95050

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Architect
187th2019 - Architect
Overall Rating: 187/199
Median Salary: $79,380

Work Environment
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190/220
Stress
Very High
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Growth
Very Poor
183/220