Senior Staff RTL Design Engineer - PPA

Intel
Santa Clara, CA
  • Job Code
    JR0185976
Job Description

Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products. DE's mission is to enable all Intel product design teams to get to market faster with leadership products. The Design Technology Pathfinding (DTP) organization within DE, is chartered to identify and drive key strategic initiatives in the pathfinding of technologies for the future. 

As a holistic co-optimization across the Product Stack from System architecture to silicon as we extend Design Technology Co-Optimization (DTCO) to System Technology Co-Optimization (STCO). The job requires partnering and leveraging domain experts across Intel's Eco-System 


Your responsibilities may include, but not be limited to: 

  • Evaluating new 3D Arch requirements. 

  • Advanced RISC Machines (ARM) IP configuration 

  • Identify 3D architecture configurations and die partition for best PPA 

  • RTL coding Verilog system Verilog logic simulation synthesis and timing analysis 

  • Validate design and micro-architectural implementation and assumptions 

  • Use case analysis Performance and Power optimizations explorations and analysis 

  • Participate in Silicon debug 


Important behavior attributes: 

  • Analytical and problem-solving skills 

  • Verbal/written communication skills 

  • Effective team player with continuous learning mindset



Qualifications

You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Bachelor's in Electrical, Computer Engineering with 8+ years of semiconductor work experience. 


Direct hands-on experience in the following areas: 

  • ARM-based Systems 

  • RTL design

  • Verilog Compiler Simulator (VCS) OR Verdi - Synopsys 

  • Synthesis

  • Low-power design and Multiple clock domain design 


Preferred Qualifications: 

Master's in Electrical, Computer Engineering with 6+ years of semiconductor work experience. 

  • Micro-architecture trade-offs and documentation 

  • Design for Test (DFT) and Design for Debug (DFD) 

  • Pre-silicon and post-silicon validation

#designenablement 
@designenablemnt 
#LI-JR1 

Inside this Business Group

Manufacturing and Product Engineering (MPE) is responsible for test development across product segments, supporting 95% of Intel's revenue. We deliver comprehensive pre-production test suites and component/physical debug capabilities to enable high quality, high volume manufacturing.



Other Locations
US, Arizona, Phoenix; US, Oregon, Hillsboro;



Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Senior Staff RTL Design Engineer - PPA

Intel
Santa Clara, CA

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