Senior SoC Physical Design Engineer

Austin, TX 78701
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Job Description

In this role you will be a key member of a team participating in the design of a future generation Intel E-Core microprocessor.

Responsibilities for this position will include but not be limited to:

  • Critical path analysis and identification of logic structures requiring custom design and layout for timing optimization
  • Block floor planning
  • Clock tree synthesis
  • RTL to gate level netlist generation through synthesis placement clock tree synthesis and route flows
  • Static timing analysis and convergence flows
  • Validation of physical design including timing electrical rules DRCLVS Noise electro migration checks
  • Formal equivalence verification
  • Scripting to automate tasks and improve debug efficiency
  • Oversee definition design verification and documentation for SoC System on a Chip development
  • Determine architecture design logic design and system simulation
  • Define module interfaces formats for simulation
  • Perform Logic design for integration of cell libraries functional units and subsystems into SoC full chip designs Register Transfer Level coding and simulation for SoCs
  • Contribute to the development of multidimensional designs involving the layout of complex integrated circuits
  • Perform all aspects of the SoC design flow from high level design to synthesis place and route timing and power to create a design database that is ready for manufacturing
  • Analyze equipment to establish operation infrastructure conduct experimental tests and evaluate results
  • Review vendor capability to support development

The ideal candidate will also exhibit behavioral traits that indicate:

  • Works well in a team and is productive under aggressive schedules
  • Excellent written and verbal communication skills
  • Self-motivation and good organizational skills


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

The candidate must have a Bachelor's degree in Computer or Electrical Engineering and 4+ years of work experience - OR - a Master's degree in Computer or Electrical Engineering and 3+ years of work experience.

7+ years experience with:

  • Physical design with synthesis and APR flows
  • Chip physical design verification including FEV timing electrical rules DRCLVS Noise RV
  • DC ICC2 Fusion PrimeTime PTSI Conformal LEC Redhawk Electrical rule checker and Verification Compiler
  • TCL and Perl coding

Inside this Business Group

The Devices Development Group (DDG) is a global organization focused on the development and integration of SOCs, critical IPs including Atom and chipsets that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Other Locations

US, Oregon, Hillsboro

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Senior SoC Physical Design Engineer

Austin, TX 78701

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19th2019 - Physicist
Overall Rating: 19/199
Median Salary: $117,220

Work Environment
Very Good