Senior Post Silicon Debug Engineer

Intel
Folsom, CA 95630
  • Job Code
    JR0201580
Job Description

The world is transforming - and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower peoples digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver solutions for products that impact customers lives? If so, Come join us to do something wonderful!

The IP Engineering Group is responsible for developing leadership IPs that power winning products for our Intel Foundry Customers and Intel. IPG develops a broad portfolio of IPs, including standard cell libraries, memory compilers, network on chip, audio and sensing IP, PLLs, IO controllers and PHYs for serial and parallel IO as DDR/LPDDR, PCIe, USB, Die 2 Die and Ethernet Serdes etc. The Customer Engineering Group within IPG will be a dynamic and versatile team of engineers who directly engage with both the IP design teams and internal and external customers in all phases of IP development (architecture, pre silicon, post silicon execution, validation, and debug). These engineers will embody customer obsession by quickly resolving customer issues and providing hands on debug on a wide range of technical issues spanning all the domains like logic and circuit design, timing, board, scripts, testing environment and end point issues etc.

This position is exciting and challenging to exercise your cross-communication skills across internal and external Intel Foundry Services. Your responsibilities will include but are not limited to:

  • Lead the silicon Power On activities for test chips and products from IP perspectives
  • Engage in the upfront identification of silicon issue and triage to isolate the problematic area
  • Investigate, debug and disposition customer bugs/sightings in a responsive and timely manner
  • Carry out pre silicon and post silicon reproduction of the issue and work towards to root cause with failure analysis etc.
  • Work closely with customers and IP design teams to provide pre silicon and/or post silicon design characterizations
  • Writing the debug test codes in python, SV, board design reviews, Post silicon collaterals reviews etc.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications


Candidate must have a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 3+ years of experience in/with: - OR - a Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 2+ years of experience in/with: - OR - a PhD Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

  • Electrical or Functional Post Silicon validation and debug with either serial IOs (PCIe, USB, SATA, TypeC, Ethernet) or parallel IOs(DDR, LPDDR, Die2Die)
  • Lab hardware and software
  • Oscilloscopes, Logic Analyzers, Protocol analyzers and BERTs
  • At least one or more industry standard IO specifications like DDR, LPDDR, PCIE, USB, USB TypeC, Die2Die, Ethernet, etc. Either PHY or Controller experience


Preferred Qualifications

Experience in/with:

  • Design team and customers to solve issues either remotely or onsite
  • Signal integrity and power delivery
  • Pre silicon design or simulation experience in logic, circuits, firmware or MRC and mixed signal validation

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.



Other Locations

US, Arizona, Phoenix;US, California, Santa Clara;US, Oregon, Hillsboro


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Before you go...

Our free job seeker tools include alerts for new jobs, saving your favorites, optimized job matching, and more! Just enter your email below.

Share this job:

Senior Post Silicon Debug Engineer

Intel
Folsom, CA 95630

Join us to start saving your Favorite Jobs!

Sign In Create Account