Senior Physical Design Manager

Intel
Santa Clara, CA 95050
  • Job Code
    JR0188138
Job Description

The Xeon Engineering Group (XEG) delivers world class Server SOCs for Intel and has a track record of being one of the premier organizations within Intel, having delivered multiple generation of Servers. XEG has multiple products in development. We are excited for what is ahead in Intel's product leadership. Come join us in this exciting journey to redefine the Backend methodologies  and lead a world class Physical design team.

In this role responsibilities include although not limited to:

  • IP physical development, leadership, and execution at the lead level
  • Key part of IP physical design team leadership
  • Drive design methodologies and key functional areas providing technical leadership and guidance
  • Drive and own hands-on design convergence and quality for large blocks clusters from RTL to GDS, PnR, Timing EMIR PDV etc.
  • Work extensively with implementation and RTL teams to help optimize, converge the designs and drive PPA improvements
  • Ensure cross teams communications with Logic and Arch Teams and also with FullChip Timing CAD and Integration Teams
  • Influence tools flows and overall RTL to GDS2 physical design methodology with a data driven approach
  • Technical lead and mentor for junior engineers in the team and drive vendor teams to achieve various milestone goals


Qualifications

Minimum Qualifications

The candidate must have a Bachelor's degree in Electrical Engineering or Computer Engineering or Computer Science and 10+ years of experience in the below listed qualifications: - OR - a Master's degree in Electrical Engineering or Computer Engineering or Computer Science and 7+ years of experience in the below listed qualifications: - OR - a PhD in Electrical Engineering or Computer Engineering or Computer Science and 5+ years of experience in the below listed qualifications:

  • Structural design
  • Physical Design optimization implementation and verification of CPU, SOC, High speed designs
  • Leading physicals design teams

Preferred Qualifications

Experience in:

  • DDR Memory Controller implementation
  • EDA Tools specifically ICC2, DC -Design Compiler, Fusion Compiler, PrimeTime or the equivalency in Cadence Tools
  • Place/Route tools, Synthesis tools etc.
  • STA and power analysis tools
  • Programming and scripting Perl TCL with strong fundamentals
  • LEC, FEV PDV EMIR
  • Industry standards and practices in Physical Design including Physically aware synthesis Floorplanning and Place Route

Inside this Business Group

Xeon Performance Group (XPG) delivers custom server SoC design solutions to our data center customers. It is chartered to deliver data centric silicon that is high-performing, cost-effective, high-quality, and on schedule in way that increases market share and drives the best solutions for our customers.


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Senior Physical Design Manager

Intel
Santa Clara, CA 95050

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