Senior Physical Design Implementation Engineer

Intel
Phoenix, AZ 85003
  • Job Code
    JR0190406
  • Jobs Rated
    19th
Job Description

Join Intel-and engineer the future.
Intel is in the midst of an exciting transformation, with a vision to create and extend computing technology to connect and enrich the lives of every person on Earth. So join us-and help us create the next generation of technologies that will shape the future for decades to come.

Position Description
Intel IP Engineering Group invites you to be part of a senior team dedicated to developing and leading backend design methodology for ground-breaking high-performance IPs. This is a unique chance to join an experienced team, as we continue transforming ourselves into the IP supplier of choice for flagship Intel SoCs. Current efforts include design innovations to achieve best in class performance across a broad scope of IPs and process technologies, as well as defining and driving methodology advancement across the IP execution teams.

What you'll do
As an SoC Design Engineer, this position specifically focuses on physical design implementation methodology for structural design and serving as a technical expert driving engagement with partner organizations, vendors, and the methodology team. A knowledge of the design flows end-to-end as well as a working knowledge of design automation functions is also required.

You must have hands-on and in-depth knowledge of SoC Physical design flow from high level design to synthesis, place and route, timing and power, to creating a design database that is ready for manufacturing. You should also have the technical expertise, knowledge, and experience to:

  • Lead and mentor junior engineers in specific physical design domains
  • Effectively communicate with larger numbers of design engineers, providing high quality documentation and presentations
  • Guide and collaborate with partner domains like Logic, Design Automation, test, etc., to optimize for convergence
  • Coordinate with other methodology disciplines to ensure a seamless design execution approach


The responsibilities will include but not limited to:

  • Logic synthesis and Auto Place and Route for IP blocks, with deep expertise in place and route tools (Fusion/Innovus)
  • Evaluate low power techniques and power reduction opportunities the automation may be able to provide
  • Perform clock distribution design and analysis
  • Tune application options, and make recommendations for execution on the optimal settings based on design needs
  • Evaluate and explore new automation technology, and advocate for efficiency improvements
  • Drive technical activities of physical design during all phases of execution


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
The candidate must have a Bachelor's degree in Electrical/Computer Engineering or other related field of study and 6+ years of experience -OR- Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 4+ years of experience in:

  • SOC/IP physical design
  • Floor planning and routing
  • Physical design convergence and tape-in
  • Interconnect design and analysis
  • Translation of architectural specification into physical domain
  • Layout design
  • RTL/Logic design (Verilog, VCS, etc.)


Preferred Qualifications:

  • Multiple automation vendors
  • Leading process nodes

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.



Other Locations

US, California, Santa Clara;US, Colorado, Fort Collins;US, Massachusetts, Hudson;US, Oregon, Hillsboro


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Annual Salary Range for jobs which could be performed in US, Colorado:
$130,020.00-$195,420.00


Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here

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Senior Physical Design Implementation Engineer

Intel
Phoenix, AZ 85003

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Physicist
19th2019 - Physicist
Overall Rating: 19/199
Median Salary: $117,220

Work Environment
Very Good
44/220
Stress
Low
78/220
Growth
Good
60/220