Senior Physical Design Engineer

Santa Clara, CA 95050
  • Job Code
Job Description

Xeon Performance Group (XPG) delivers world class Server SOCs for Intel and has a track record of being one of the premier organization within Intel having delivered multiple generation of Servers. XPG has multiple products in development and has a strong roadmap ahead for Intel's product leadership. Come join us in this exciting journey to re-define the Backend methodologies, efficiency and be an integral part of the XPG Physical design and Backend teams.

In this role responsibilities include, although not limited to:

  • Drive design methodologies and key functional areas providing technical leadership and guidance
  • Drive and own hands-on design convergence and quality for large blocks, clusters from RTL to GDS [Synthesis, Place & Route, Timing, EMIR, PDV etc].
  • Work extensively with implementation and RTL teams to help optimize/converge the designs and drive PPA improvements
  • Ensure cross teams' communications with Logic and Arch Teams and also with Full-Chip Timing, CAD and Integration Teams
  • Influence tools, flows and overall RTL to GDS2 physical design methodology with a data driven approach
  • Technical lead for junior engineers in the team and drive vendor teams to achieve various milestone goals


You must possess the below minimum qualifications to be initially considered for this position Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates

Minimum Qualifications:

The candidate must have a Bachelors degree in Electrical/Computer Engineering or Computer Science and 6+ years of experience OR a Masters degree in Electrical/Computer Engineering or Computer Science and 5+ years of experience OR a PhD in ElectricalComputer Engineering or Computer Science and 2+ years of experience with:

  • Structural design and verification in large microprocessor designs
  • Lead technically drive design methodologies and be able to technically lead a domainteam
  • Cross teams communications with logic and arch teams and also with full chip timing and integration teams
  • Knowledge in EDA Tools specifically ICC2 DCDesign Compiler PrimeTime or the equivalency in Cadence Tools

Preferred Qualifications:

8+ years of experience in:

  • Proficiency in using STA and power analysis tools
  • Proficiency in programming and scripting (Perl, TCL) with strong fundamentals
  • Proficiency in LEC/FEV, PDV, EMIR
  • Deep Knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route

Inside this Business Group

Xeon Performance Group (XPG) delivers custom server SoC design solutions to our data center customers. It is chartered to deliver data centric silicon that is high-performing, cost-effective, high-quality, and on schedule in way that increases market share and drives the best solutions for our customers.

Other Locations

US, Massachusetts, Hudson;US, Oregon, Hillsboro

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Senior Physical Design Engineer

Santa Clara, CA 95050

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