Senior Memory Sub System Pre Silicon Verification Engineer

Intel
San Jose, CA 95113
  • Job Code
    JR0175795
Job Description

As a Memory Controller and IO Sub-System Verification Technical Lead, candidate will lead the team from Specification to product, including Tech Readiness, verification test bench and test strategy, reviews, FW and DFX verification enablement. Candidate will be the face of the organization to drive verification of memory controller with interface to all design domains.

In this position, your responsibilities will include but not be limited to:

  • Define verification strategy for high performance and low power DDR I/O controller and highly configurable IO Sub-system. DDR technologies spans from DDR4, DDR5, LPDDR4 and LPDDR5.

  • Architect and Develop pre-silicon verification OVM/UVM based environment/test-bench and test sequences.

  • Evaluate and Develop BFMs to interface with the IP with the capability of monitoring transaction and checking protocol.

  • Define verification strategies, methodologies and write complete test plans.

  • Develop testcases, assertions and functional coverage using System Verilog.

  • Setup and run GLS to verify the asynchronous and multi-cycle paths.

  • Debug test failures, and implement corrective measures for the failing conditions.

  • Analyze and drive functional coverage.

  • Develop automated tools or scripts for pre-silicon verification efficiency improvement.

  • Collaborate with SOC/Sub-system on IP integration issues.

  • Collaborate closely with micro-architects and logic/analog designers.

The successful candidate requires a strong technical background in micro-architecture design, logic and verification methodology. They need to be someone who is passionate about working in a dynamic environment where the expectation is to contribute in any activity that makes the business successful. Candidate must have strong communication skills, teamwork, be a self-starter, and can mange a geographically dispersed and a dynamic work environment.


Qualifications

You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Education

Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Minimum Qualifications

10+ years of total experience inclusive of

  • Pre-Silicon Verification

  • Experience in using verification tools such as VCS, DVE, Verdi, etc.

  • Experience in JEDEC specification (e.g. DDR 4/5)

Preferred Qualifications

  • SystemVerilog OVM/UVM and verification methodologies

  • BFMs/VIPs, coding experience that includes logic+behavioral modelling SV coding

  • Experience in Formal Property Verification method

  • High Speed I/O Design and Mixed signal design

  • Experience in IP integration

  • Experience in power aware design, UPF , multi-power domain checks.

  • Experience in problem solving, debugging various simulation failures, and formal verification.

  • Experience with post silicon DDR debug and IO training

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.



Other Locations

US, California, Folsom;US, California, Santa Clara;US, Texas, Austin



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Senior Memory Sub System Pre Silicon Verification Engineer

Intel
San Jose, CA 95113

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