Senior Member of Technical Staff - Signal and Power integrity Engineer

Intel
San Jose, CA 95113
  • Job Code
    JR0186581
Job Description

We are a global leader, creating world-changing technology that enables progress and enriches lives. Intel is at the intersection of several technology inflections - artificial intelligence, 5G network transformation, and the rise of the intelligent edge- that together will shape the future of technology.

As a member of Intel's Programmable Solutions Group
(PSG), in this role the candidate will use knowledge of Signal integrity and power integrity to analyze high-speed interfaces and enable good design of Power Distribution Networks (PDN). The candidate will interface with other teams related to board design and packaging to lead efforts at a system level in enabling customers, both internal and external, to use the Structured ASIC technology. The candidate should also be familiar with lab measurements and debug.

Structured ASIC team:

This is a structured ASIC team under Intel's PSG is targeting 5G, cloud computing and high-end consumer application space.
Intel eASIC devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs bridging the gap between FPGA and Custom ASIC.

Learn more about us:


Responsibilities:

  • Signal Integrity analysis of high-speed interfaces.
  • Eye diagrams and jitter analysis via simulation and model analysis.
  • Power integrity analysis for board designs and packages.
  • Layout extraction, PDN analysis etc., to enable precise recommendations in terms of decoupling strategies.
  • IO power domain analysis and provide detailed simulation on Simultaneous Switching Noise/Output (SSN/SSO).
  • Document guidelines for customers for both layouts to achieve best performance - PDN, cross talk noise analysis.
  • Provide support for customers as need arises in their Printed Circuit Board (PCB) designs.
  • Work in the lab to confirm some of the simulation findings.
  • Train and provide engineering support to Intel's worldwide customers and Applications team.


Qualifications

Minimum Education Requirements
Bachelors' degree in Electrical Engineering, Electrical Electronics or Computer Engineering with 10 plus years of experience or Masters' degree in Electrical Engineering, Electrical Electronics or Computer Engineering with 7 plus years of experience.

Minimum Qualifications

7+ years of experience in the following:

  • Power integrity and signal integrity analysis using tools like HSPICE, Sigrity, PowerSI, Keysight ADS, etc.
  • IBIS-AMI models with skills to analyze simulation results and provide guidelines on the channel characteristics and transceiver behavior.
  • High-speed IO and SERDES and its applications. 
  • SI Concepts, including sources and causes of noise and jitter.
  • Transmission line theory, electro magnetics, layout - both packaging and PCB.
  • Scripting experience with either Python, Matlab or Perl. 
  • Testing equipment, such as high-speed oscilloscopes, BERTs and VNA.

Preferred Qualifications

Experience in analog and digital design.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Senior Member of Technical Staff - Signal and Power integrity Engineer

Intel
San Jose, CA 95113

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