Senior Mask Designer

Intel
San Jose, CA 95113
  • Job Code
    JR0179621
Job Description

The mission of Intels Programmable Solutions Group (PSG) is to drive the future for FPGAs and Structured ASICs technology/solutions around the globe.

With the San Jose Custom Layout Team, you'll be surrounded by some of the brightest minds/engineers in the world. We are responsible for the development and preparation of multidimensional layouts and detailed drawings of semiconductor devices and microelectronic package assemblies. Our responsibilities may be directed at a specific point in the design cycle or vary as the project progresses through the design stage. Our assignments are somewhat complex in nature. The work will be performed within generally defined parameters and judgment is required in resolving moderately complex problems. We normally receive general instructions on routine work, detailed instructions on new work.

As a Senior Mask Designer, you will also be responsible for:

  • Development and creation of exceptional quality custom and semi-custom analog layouts

  • Apply experience in layout to appropriately address ANT, ESD, LU, EM, reliability, and thermal effects.

  • Layout floor-planning, power plan, routing plan, hierarchical layout assembly, custom cell design, optimized cell sharing, and final layout generation

  • Provide and maintain reliable layout schedules

  • Lead a design: delegate daily tasks, provide technical guidance and review layout quality


Qualifications

You must possess the below minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

  • 3+ years of experience in an analog layout role

  • Experience in advanced technology nodes, 20nm and below, and finFet technologies

Preferred Qualifications

  • Experience in layout Floor-planning, power plan, routing plan, LVS, DRC, ANT, ESD, LU, RV.

  • Experience with analog structures such as differential pairs and current mirror, layout skills in matching, multiple power domain, high current, high voltage, and high-speed designs.

  • Experience providing and maintaining layout schedules

  • Experience leading a design: delegate daily tasks, provide technical guidance and review layout quality

  • 10+ years of experience in an analog layout role

  • Experienced with Virtuoso tool usage

  • Experienced with Unix

  • Experience in programming

  • Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field


This position is not eligible for Intel immigration sponsorship.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.



Other Locations

US, California, Santa Clara



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Senior Mask Designer

Intel
San Jose, CA 95113

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