Senior IP Design Formal Validation

Intel
Hillsboro, OR 97123
  • Job Code
    JR0181921
Job Description

The world is transforming and so is Intel! 

Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower peoples digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver IP solutions for products that impact customers lives? If so, come join us to do something wonderful!

Advanced IO virtualization is at the forefront of technological innovations that span across segments from smart devices, personal computers, servers and enterprises, to high performance computing. The IO Memory Management Unit IP team is looking for a passionate design verification engineer with background in state-of-the-art pre-silicon verification techniques. This position provides a unique opportunity to learn, grow, and influence IP verification collateral including but not limited to Formal Property Verification , & scalable test-environment etc. The candidate will be part of a silicon design team chartered with developing and delivering multiple generations of highly configurable IOMMU IP to multiple Intel SOCs. This is a hands on, and highly technically rewarding individual contributor role.

Responsibilities will include but not limited to:

  • Evaluations for complexity and effort for new features. Owning feature execution by writing comprehensive test plans, checking strategies, test-cases, and driving verification methodology improvements for high quality feature delivery.
  • Interact and work closely with architecture, logic design team members, to influence IP definition to simplify validation goals without compromising IP competitiveness.
  • Demonstrate ingenuity, creativity, and adeptness in defining and developing modular verification collateral.
  • Run focused technical validation work-group meetings.

 The role requires the following attributes / qualifications:

  • Should have excellent problem solving skills, written and verbal communication.
  • Hands-on Formal Property verification experience with writing System Verilog Assertions, constraints for DUT, measuring coverage etc. Exposure to industry standard formal verification tools will be a big plus.

Experience in development and deployment of verification strategies and methodologies across teams and organizations.

  • Ability to work in a dynamic environment, understand abstract concepts, and multitasking.


Qualifications

This position requires meeting the below minimum qualifications to be initially considered. Preferred qualifications are in addition to the minimum requirements and are considered a major plus.

Minimum Qualifications:

  • Candidate must have a Bachelor's degree in Electrical / Computer Engineering with 6+ years' of experience -OR- a Master's degree in Electrical / Computer Engineering with 4+ years' of experience in:
  • Formal and assertion based verification in system verilog.
  • Reading and interpreting technical specs and Register Transfer Level (RTL) code.
  • Feature evaluations for complexity and effort
  • Experience in formal tool like jasper

Preferred Qualifications: Experience in:

  • Verifying standard IO protocols like PCIE / CXL / USB / Ethernet etc.
  • Computer architecture and PCIe protocols
  • Supporting post-silicon bring up and debug.
  • Programming and scripting with C/C++/Perl/Python

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.



Other Locations

US, California, Santa Clara;US, Texas, Austin


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Senior IP Design Formal Validation

Intel
Hillsboro, OR 97123

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