Senior Fabric Logic Designer

Santa Clara, CA 95050
  • Job Code
Job Description

At Intel, we work every single day to design and manufacture silicon products that empower peoples digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver IP solutions for products that impact customers lives? If so, this might be the team for you.

In this position, you will be working within the Fabric IP team to deliver configurable interconnect fabric designs

Our design team works in close partnership with validation and automation allowing us to deliver flexible designs that are used everywhere from low power IoTG to high end server applications

We deliver all across Intel giving the team impact and exposure to different projects

Responsibilities include but not limited to:

  • Evaluating new Arch requirements
  • Writing and testing new RTL
  • Resolving timing paths
  • Debugging customer SOC failures
  • Running design checking tools
  • Making quarterly releases of new IP

In addition to the qualifications listed below the ideal candidate will also have:

  • Excellent analytical and problem-solving skills
  • Strong verbal/written communication skills
  • Effective team player with continuous learning mindset
  • Willingness to balance multiple tasks
  • Willingness to work in a fast-paced environment and have as much fun and growth as possible in the process


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications
Candidate will have Masters degree in Electrical Computer Engineering with 3+ years of direct hands on work experience in

  • Frontend RTL design
  • Validation and scripting Analysis and development of RTL to meet architecture requirements
  • Ability to make tradeoffs of area schedule power performance
  • Ability to create from scratch or leverage existing IP as needed
  • RTL coding Verilog system Verilog logic simulation synthesis and timing analysis
  • Experience with design tools Lint Synthesis CDC FV ATPG etc
  • Strong written and communication skills are essential since our team delivers to many internal customer groups that we support in deployment

Preferred requirements

  • Knowledge of various bus protocols async crossing techniques clock gating challenges
  • Experience working with cross functional and cross site teams
  • Experience creating and debugging scripts Python TCL

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Senior Fabric Logic Designer

Santa Clara, CA 95050

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