Senior Engineer - Post Silicon Debug

Intel
Folsom, CA 95630
  • Job Code
    JR0190120
Job Description

The IP Engineering Group (IPG) organization is responsible for developing leadership IPs that power-winning products for our Intel Foundry Customers and Intel. IPG develops a broad portfolio of IPs, including standard cell libraries, memory compilers, network on chip, audio and sensing IP, PLLs, IO controllers and PHYs for serial and parallel IO as DDR/LPDDR, PCIe, USB, Die 2 Die and Ethernet Serdes etc.

The Customer Engineering Group (CEG) within IPG will be a dynamic and versatile team of engineers who directly engage with both the IP design teams and internal and external customers in all phases of IP development (architecture, pre-silicon, post silicon execution, validation, and debug). These engineers will embody customer obsession by quickly resolving customer issues and providing hands on debug on a wide range of technical issues spanning all the domains like logic and circuit design, timing, board, scripts, testing environment and end point issues etc. This position is exciting and challenging to exercise your cross-communication abilities across internal and external Intel Foundry Services.

Your responsibilities will include but are not limited to:

  • Lead the silicon Power On activities for test chips and products from IP perspectives
  • Engage in the upfront identification of silicon issue and triage to isolate the problematic area.
  • Investigate, debug and disposition customer bugs/sightings in a responsive and timely manner.
  • Carry out pre silicon and post silicon reproduction of the issue and work towards to root cause with failure analysis etc...
  • Work closely with customers and IP design teams to provide pre silicon and/or post silicon design characterizations, writing the debug test codes in pythonSV, board design reviews, Post silicon collaterals reviews etc...
  • Prepare customer training materials and provide training on high level post silicon testing strategies, IP specifications, and fuse/register settings to enable effective debug.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must have a Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 4+ years of experience - OR - Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 3+ years of experience

- OR - a PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field with 1+ years of experience :

  • in Electrical or Functional Post Silicon validation, debug with either serial IOs (PCIe, USB, SATA, TypeC, Ethernet) or parallel IOs(DDR, LPDDR, Die2Die).
  • Well versed with the lab hardware and software is must. Must be proficient in using Oscilloscopes, Logic Analyzers, Protocol analyzers and BERTs.
  • Familiarity with at least one or more industry standard IO specifications like DDR, LPDDR, PCIE, USB, USB TypeC, Die2Die, Ethernet, etc. Either PHY or Controller experience is good.

Preferred Qualifications:

  • Able to work independently with design team and customers to solve issues either remotely or onsite.
  • Good understanding of signal integrity and power delivery are desired
  • Pre silicon design or simulation experience in logic, circuits, firmware or MRC and mixed signal validation will be a plus.

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.



Other Locations

US, California, Santa Clara;US, Oregon, Hillsboro


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Senior Engineer - Post Silicon Debug

Intel
Folsom, CA 95630

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